Ticket #752 (closed defect: fixed)

Opened 2 years ago

Last modified 2 years ago

Cache detection error

Reported by: Philip Owned by: jan
Priority: Should Have Milestone: Alpha 5
Component: Core engine Keywords:
Cc:

Description

Someone reports:

Assertion failed: "0"
Location: x86_x64.cpp:457 (DetectCache_CPUID4)

Call stack:

00567D5F

005691C8

0053F27B

02A000B0

0003FFA8


errno = 0 (?)
OS error = 0 (no error code was set)


Assertion failed: "dcaches.numLevels >= 2"
Location: x86_x64.cpp:698 (DetectCacheAndTLB)

Call stack:

00567D5F

005691C8

0053F27B


errno = 0 (?)
OS error = 487 (Se ha intentado tener acceso a una dirección no válida.
)


Assertion failed: "dcaches.levels[0].lineSize != 0"
Location: x86_x64.cpp:699 (DetectCacheAndTLB)

Call stack:

00567D5F

005691C8

0053F27B


errno = 0 (?)
OS error = 487 (Se ha intentado tener acceso a una dirección no válida.
)



Assertion failed: "dcaches.levels[1].lineSize != 0"
Location: x86_x64.cpp:700 (DetectCacheAndTLB)

Call stack:

00567D5F

005691C8

0053F27B


errno = 0 (?)
OS error = 487 (Se ha intentado tener acceso a una dirección no válida.
)

The relevant reported data is:

  "cpu_coresperpackage": 1, 
  "cpu_frequency": 2533000000, 
  "cpu_identifier": "    Intel Pentium 4 2.53GHz", 
  "cpu_largepagesize": 0, 
  "cpu_logicalpercore": 1, 
  "cpu_numcaches": 1, 
  "cpu_numpackages": 1, 
  "cpu_numprocs": 1, 
  "cpu_pagesize": 4096, 
  [...]
  "uname_machine": "IA-32", 
  "uname_release": "SP 2", 
  "uname_sysname": "WinXP", 
  "uname_version": "5.1.2600", 
  [...]
  "x86_caps[0]": 17408, 
  "x86_caps[1]": 3219913727, 
  "x86_caps[2]": 0, 
  "x86_caps[3]": 0, 
  "x86_dcaches": [], 
  "x86_dtlbs": [
    {
      "associativity": 255, 
      "entries": 64, 
      "level": 1, 
      "pagesize": 4096, 
      "type": 1
    }
  ], 
  "x86_family": 15, 
  "x86_icaches": [], 
  "x86_itlbs": [
    {
      "associativity": 255, 
      "entries": 128, 
      "level": 1, 
      "pagesize": 4096, 
      "type": 2
    }
  ], 
  "x86_model": 2, 
  "x86_vendor": 1

Change History

comment:1 Changed 2 years ago by jan

Bummer, that P4 doesn't support CPUID function 4. Even if it did support 0x80000006, that would only tell us about the L2$, not L1. Looks like it will be necessary to refer to the descriptors from function 2, which is a huge pain. Oh well, I might be able to tackle that tomorrow.

comment:2 Changed 2 years ago by jan

(This involved a sizable change and I'm not quite finished with it yet.)

comment:3 Changed 2 years ago by jan

  • Status changed from new to closed
  • Resolution set to fixed

(In [9074]) move cache detection into separate file. add support for CPUID.2 cache descriptors (many Bothans died to bring us this information) simplify the API - use one structure to describe cache and TLB; only one accessor for both.

HWDetect: version change, since dtlbs and itlbs are no longer distinguished

fixes #752

comment:4 Changed 2 years ago by fabio

  • Milestone changed from Backlog to Alpha 5
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