Context Navigation

Back to Ticket #2074

Ticket #2074: cpuid.txt

File cpuid.txt, 115.0 KB (added by historic_bruno, 11 years ago)
cpuid output may be of some interest

Line
1	CPU 0:
2	vendor_id = "GenuineIntel"
3	version information (1/eax):
4	processor type = primary processor (0)
5	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
6	model = 0x6 (6)
7	stepping id = 0x1 (1)
8	extended family = 0x0 (0)
9	extended model = 0x4 (4)
10	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
11	miscellaneous (1/ebx):
12	process local APIC physical ID = 0x0 (0)
13	cpu count = 0x10 (16)
14	CLFLUSH line size = 0x8 (8)
15	brand index = 0x0 (0)
16	brand id = 0x00 (0): unknown
17	feature information (1/edx):
18	x87 FPU on chip = true
19	virtual-8086 mode enhancement = true
20	debugging extensions = true
21	page size extensions = true
22	time stamp counter = true
23	RDMSR and WRMSR support = true
24	physical address extensions = true
25	machine check exception = true
26	CMPXCHG8B inst. = true
27	APIC on chip = true
28	SYSENTER and SYSEXIT = true
29	memory type range registers = true
30	PTE global bit = true
31	machine check architecture = true
32	conditional move/compare instruction = true
33	page attribute table = true
34	page size extension = true
35	processor serial number = false
36	CLFLUSH instruction = true
37	debug store = true
38	thermal monitor and clock ctrl = true
39	MMX Technology = true
40	FXSAVE/FXRSTOR = true
41	SSE extensions = true
42	SSE2 extensions = true
43	self snoop = true
44	hyper-threading / multi-core supported = true
45	therm. monitor = true
46	IA64 = false
47	pending break event = true
48	feature information (1/ecx):
49	PNI/SSE3: Prescott New Instructions = true
50	PCLMULDQ instruction = true
51	64-bit debug store = true
52	MONITOR/MWAIT = true
53	CPL-qualified debug store = true
54	VMX: virtual machine extensions = true
55	SMX: safer mode extensions = false
56	Enhanced Intel SpeedStep Technology = true
57	thermal monitor 2 = true
58	SSSE3 extensions = true
59	context ID: adaptive or shared L1 data = false
60	FMA instruction = true
61	CMPXCHG16B instruction = true
62	xTPR disable = true
63	perfmon and debug = true
64	process context identifiers = true
65	direct cache access = false
66	SSE4.1 extensions = true
67	SSE4.2 extensions = true
68	extended xAPIC support = true
69	MOVBE instruction = true
70	POPCNT instruction = true
71	time stamp counter deadline = true
72	AES instruction = true
73	XSAVE/XSTOR states = true
74	OS-enabled XSAVE/XSTOR = true
75	AVX: advanced vector extensions = true
76	F16C half-precision convert instruction = true
77	RDRAND instruction = true
78	hypervisor guest status = false
79	cache and TLB information (2):
80	0x63: unknown
81	0x03: data TLB: 4K pages, 4-way, 64 entries
82	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
83	0xff: cache data is in CPUID 4
84	0xb5: unknown
85	0xf0: 64 byte prefetching
86	0xc1: unknown
87	processor serial number: 0004-0661-0000-0000-0000-0000
88	deterministic cache parameters (4):
89	--- cache 0 ---
90	cache type = data cache (1)
91	cache level = 0x1 (1)
92	self-initializing cache level = true
93	fully associative cache = false
94	extra threads sharing this cache = 0x1 (1)
95	extra processor cores on this die = 0x7 (7)
96	system coherency line size = 0x3f (63)
97	physical line partitions = 0x0 (0)
98	ways of associativity = 0x7 (7)
99	WBINVD/INVD behavior on lower caches = false
100	inclusive to lower caches = false
101	complex cache indexing = false
102	number of sets - 1 (s) = 63
103	--- cache 1 ---
104	cache type = instruction cache (2)
105	cache level = 0x1 (1)
106	self-initializing cache level = true
107	fully associative cache = false
108	extra threads sharing this cache = 0x1 (1)
109	extra processor cores on this die = 0x7 (7)
110	system coherency line size = 0x3f (63)
111	physical line partitions = 0x0 (0)
112	ways of associativity = 0x7 (7)
113	WBINVD/INVD behavior on lower caches = false
114	inclusive to lower caches = false
115	complex cache indexing = false
116	number of sets - 1 (s) = 63
117	--- cache 2 ---
118	cache type = unified cache (3)
119	cache level = 0x2 (2)
120	self-initializing cache level = true
121	fully associative cache = false
122	extra threads sharing this cache = 0x1 (1)
123	extra processor cores on this die = 0x7 (7)
124	system coherency line size = 0x3f (63)
125	physical line partitions = 0x0 (0)
126	ways of associativity = 0x7 (7)
127	WBINVD/INVD behavior on lower caches = false
128	inclusive to lower caches = false
129	complex cache indexing = false
130	number of sets - 1 (s) = 511
131	--- cache 3 ---
132	cache type = unified cache (3)
133	cache level = 0x3 (3)
134	self-initializing cache level = true
135	fully associative cache = false
136	extra threads sharing this cache = 0xf (15)
137	extra processor cores on this die = 0x7 (7)
138	system coherency line size = 0x3f (63)
139	physical line partitions = 0x0 (0)
140	ways of associativity = 0xb (11)
141	WBINVD/INVD behavior on lower caches = false
142	inclusive to lower caches = true
143	complex cache indexing = true
144	number of sets - 1 (s) = 8191
145	--- cache 4 ---
146	cache type = unified cache (3)
147	cache level = 0x4 (4)
148	self-initializing cache level = true
149	fully associative cache = false
150	extra threads sharing this cache = 0xf (15)
151	extra processor cores on this die = 0x7 (7)
152	system coherency line size = 0x3f (63)
153	physical line partitions = 0xf (15)
154	ways of associativity = 0xf (15)
155	WBINVD/INVD behavior on lower caches = false
156	inclusive to lower caches = false
157	complex cache indexing = true
158	number of sets - 1 (s) = 8191
159	MONITOR/MWAIT (5):
160	smallest monitor-line size (bytes) = 0x40 (64)
161	largest monitor-line size (bytes) = 0x40 (64)
162	enum of Monitor-MWAIT exts supported = true
163	supports intrs as break-event for MWAIT = true
164	number of C0 sub C-states using MWAIT = 0x0 (0)
165	number of C1 sub C-states using MWAIT = 0x2 (2)
166	number of C2 sub C-states using MWAIT = 0x1 (1)
167	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
168	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
169	Thermal and Power Management Features (6):
170	digital thermometer = true
171	Intel Turbo Boost Technology = true
172	ARAT always running APIC timer = true
173	PLN power limit notification = true
174	ECMD extended clock modulation duty = true
175	PTM package thermal management = true
176	digital thermometer thresholds = 0x2 (2)
177	ACNT/MCNT supported performance measure = true
178	ACNT2 available = false
179	performance-energy bias capability = true
180	extended feature flags (7):
181	FSGSBASE instructions = true
182	BMI instruction = true
183	SMEP support = true
184	enhanced REP MOVSB/STOSB = true
185	INVPCID instruction = true
186	Direct Cache Access Parameters (9):
187	PLATFORM_DCA_CAP MSR bits = 0
188	Architecture Performance Monitoring Features (0xa/eax):
189	version ID = 0x3 (3)
190	number of counters per logical processor = 0x4 (4)
191	bit width of counter = 0x30 (48)
192	length of EBX bit vector = 0x7 (7)
193	Architecture Performance Monitoring Features (0xa/ebx):
194	core cycle event not available = false
195	instruction retired event not available = false
196	reference cycles event not available = false
197	last-level cache ref event not available = false
198	last-level cache miss event not avail = false
199	branch inst retired event not available = false
200	branch mispred retired event not avail = false
201	Architecture Performance Monitoring Features (0xa/edx):
202	number of fixed counters = 0x3 (3)
203	bit width of fixed counters = 0x30 (48)
204	x2APIC features / processor topology (0xb):
205	--- level 0 (thread) ---
206	bits to shift APIC ID to get next = 0x1 (1)
207	logical processors at this level = 0x2 (2)
208	level number = 0x0 (0)
209	level type = thread (1)
210	extended APIC ID = 0
211	--- level 1 (core) ---
212	bits to shift APIC ID to get next = 0x4 (4)
213	logical processors at this level = 0x8 (8)
214	level number = 0x1 (1)
215	level type = core (2)
216	extended APIC ID = 0
217	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
218	XSAVE features (0xd/0):
219	XCR0 lower 32 bits valid bit field mask = 0x00000007
220	bytes required by fields in XCR0 = 0x00000340 (832)
221	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
222	XCR0 upper 32 bits valid bit field mask = 0x00000000
223	YMM features (0xd/2):
224	YMM save state byte size = 0x00000100 (256)
225	YMM save state byte offset = 0x00000240 (576)
226	LWP features (0xd/0x3e):
227	LWP save state byte size = 0x00000000 (0)
228	LWP save state byte offset = 0x00000000 (0)
229	extended feature flags (0x80000001/edx):
230	SYSCALL and SYSRET instructions = true
231	execution disable = true
232	1-GB large page support = true
233	RDTSCP = true
234	64-bit extensions technology available = true
235	Intel feature flags (0x80000001/ecx):
236	LAHF/SAHF supported in 64-bit mode = true
237	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
238	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
239	instruction # entries = 0x0 (0)
240	instruction associativity = 0x0 (0)
241	data # entries = 0x0 (0)
242	data associativity = 0x0 (0)
243	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
244	instruction # entries = 0x0 (0)
245	instruction associativity = 0x0 (0)
246	data # entries = 0x0 (0)
247	data associativity = 0x0 (0)
248	L1 data cache information (0x80000005/ecx):
249	line size (bytes) = 0x0 (0)
250	lines per tag = 0x0 (0)
251	associativity = 0x0 (0)
252	size (Kb) = 0x0 (0)
253	L1 instruction cache information (0x80000005/edx):
254	line size (bytes) = 0x0 (0)
255	lines per tag = 0x0 (0)
256	associativity = 0x0 (0)
257	size (Kb) = 0x0 (0)
258	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
259	instruction # entries = 0x0 (0)
260	instruction associativity = L2 off (0)
261	data # entries = 0x0 (0)
262	data associativity = L2 off (0)
263	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
264	instruction # entries = 0x0 (0)
265	instruction associativity = L2 off (0)
266	data # entries = 0x0 (0)
267	data associativity = L2 off (0)
268	L2 unified cache information (0x80000006/ecx):
269	line size (bytes) = 0x40 (64)
270	lines per tag = 0x0 (0)
271	associativity = 8-way (6)
272	size (Kb) = 0x100 (256)
273	L3 cache information (0x80000006/edx):
274	line size (bytes) = 0x0 (0)
275	lines per tag = 0x0 (0)
276	associativity = L2 off (0)
277	size (in 512Kb units) = 0x0 (0)
278	Advanced Power Management Features (0x80000007/edx):
279	temperature sensing diode = false
280	frequency ID (FID) control = false
281	voltage ID (VID) control = false
282	thermal trip (TTP) = false
283	thermal monitor (TM) = false
284	software thermal control (STC) = false
285	100 MHz multiplier control = false
286	hardware P-State control = false
287	TscInvariant = true
288	Physical Address and Linear Address Size (0x80000008/eax):
289	maximum physical address bits = 0x27 (39)
290	maximum linear (virtual) address bits = 0x30 (48)
291	maximum guest physical address bits = 0x0 (0)
292	Logical CPU cores (0x80000008/ecx):
293	number of CPU cores - 1 = 0x0 (0)
294	ApicIdCoreIdSize = 0x0 (0)
295	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
296	(multi-processing method): Intel leaf 0xb
297	(APIC widths synth): CORE_width=4 SMT_width=1
298	(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
299	(synth) = Intel Core (unknown model)
300	CPU 1:
301	vendor_id = "GenuineIntel"
302	version information (1/eax):
303	processor type = primary processor (0)
304	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
305	model = 0x6 (6)
306	stepping id = 0x1 (1)
307	extended family = 0x0 (0)
308	extended model = 0x4 (4)
309	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
310	miscellaneous (1/ebx):
311	process local APIC physical ID = 0x2 (2)
312	cpu count = 0x10 (16)
313	CLFLUSH line size = 0x8 (8)
314	brand index = 0x0 (0)
315	brand id = 0x00 (0): unknown
316	feature information (1/edx):
317	x87 FPU on chip = true
318	virtual-8086 mode enhancement = true
319	debugging extensions = true
320	page size extensions = true
321	time stamp counter = true
322	RDMSR and WRMSR support = true
323	physical address extensions = true
324	machine check exception = true
325	CMPXCHG8B inst. = true
326	APIC on chip = true
327	SYSENTER and SYSEXIT = true
328	memory type range registers = true
329	PTE global bit = true
330	machine check architecture = true
331	conditional move/compare instruction = true
332	page attribute table = true
333	page size extension = true
334	processor serial number = false
335	CLFLUSH instruction = true
336	debug store = true
337	thermal monitor and clock ctrl = true
338	MMX Technology = true
339	FXSAVE/FXRSTOR = true
340	SSE extensions = true
341	SSE2 extensions = true
342	self snoop = true
343	hyper-threading / multi-core supported = true
344	therm. monitor = true
345	IA64 = false
346	pending break event = true
347	feature information (1/ecx):
348	PNI/SSE3: Prescott New Instructions = true
349	PCLMULDQ instruction = true
350	64-bit debug store = true
351	MONITOR/MWAIT = true
352	CPL-qualified debug store = true
353	VMX: virtual machine extensions = true
354	SMX: safer mode extensions = false
355	Enhanced Intel SpeedStep Technology = true
356	thermal monitor 2 = true
357	SSSE3 extensions = true
358	context ID: adaptive or shared L1 data = false
359	FMA instruction = true
360	CMPXCHG16B instruction = true
361	xTPR disable = true
362	perfmon and debug = true
363	process context identifiers = true
364	direct cache access = false
365	SSE4.1 extensions = true
366	SSE4.2 extensions = true
367	extended xAPIC support = true
368	MOVBE instruction = true
369	POPCNT instruction = true
370	time stamp counter deadline = true
371	AES instruction = true
372	XSAVE/XSTOR states = true
373	OS-enabled XSAVE/XSTOR = true
374	AVX: advanced vector extensions = true
375	F16C half-precision convert instruction = true
376	RDRAND instruction = true
377	hypervisor guest status = false
378	cache and TLB information (2):
379	0x63: unknown
380	0x03: data TLB: 4K pages, 4-way, 64 entries
381	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
382	0xff: cache data is in CPUID 4
383	0xb5: unknown
384	0xf0: 64 byte prefetching
385	0xc1: unknown
386	processor serial number: 0004-0661-0000-0000-0000-0000
387	deterministic cache parameters (4):
388	--- cache 0 ---
389	cache type = data cache (1)
390	cache level = 0x1 (1)
391	self-initializing cache level = true
392	fully associative cache = false
393	extra threads sharing this cache = 0x1 (1)
394	extra processor cores on this die = 0x7 (7)
395	system coherency line size = 0x3f (63)
396	physical line partitions = 0x0 (0)
397	ways of associativity = 0x7 (7)
398	WBINVD/INVD behavior on lower caches = false
399	inclusive to lower caches = false
400	complex cache indexing = false
401	number of sets - 1 (s) = 63
402	--- cache 1 ---
403	cache type = instruction cache (2)
404	cache level = 0x1 (1)
405	self-initializing cache level = true
406	fully associative cache = false
407	extra threads sharing this cache = 0x1 (1)
408	extra processor cores on this die = 0x7 (7)
409	system coherency line size = 0x3f (63)
410	physical line partitions = 0x0 (0)
411	ways of associativity = 0x7 (7)
412	WBINVD/INVD behavior on lower caches = false
413	inclusive to lower caches = false
414	complex cache indexing = false
415	number of sets - 1 (s) = 63
416	--- cache 2 ---
417	cache type = unified cache (3)
418	cache level = 0x2 (2)
419	self-initializing cache level = true
420	fully associative cache = false
421	extra threads sharing this cache = 0x1 (1)
422	extra processor cores on this die = 0x7 (7)
423	system coherency line size = 0x3f (63)
424	physical line partitions = 0x0 (0)
425	ways of associativity = 0x7 (7)
426	WBINVD/INVD behavior on lower caches = false
427	inclusive to lower caches = false
428	complex cache indexing = false
429	number of sets - 1 (s) = 511
430	--- cache 3 ---
431	cache type = unified cache (3)
432	cache level = 0x3 (3)
433	self-initializing cache level = true
434	fully associative cache = false
435	extra threads sharing this cache = 0xf (15)
436	extra processor cores on this die = 0x7 (7)
437	system coherency line size = 0x3f (63)
438	physical line partitions = 0x0 (0)
439	ways of associativity = 0xb (11)
440	WBINVD/INVD behavior on lower caches = false
441	inclusive to lower caches = true
442	complex cache indexing = true
443	number of sets - 1 (s) = 8191
444	--- cache 4 ---
445	cache type = unified cache (3)
446	cache level = 0x4 (4)
447	self-initializing cache level = true
448	fully associative cache = false
449	extra threads sharing this cache = 0xf (15)
450	extra processor cores on this die = 0x7 (7)
451	system coherency line size = 0x3f (63)
452	physical line partitions = 0xf (15)
453	ways of associativity = 0xf (15)
454	WBINVD/INVD behavior on lower caches = false
455	inclusive to lower caches = false
456	complex cache indexing = true
457	number of sets - 1 (s) = 8191
458	MONITOR/MWAIT (5):
459	smallest monitor-line size (bytes) = 0x40 (64)
460	largest monitor-line size (bytes) = 0x40 (64)
461	enum of Monitor-MWAIT exts supported = true
462	supports intrs as break-event for MWAIT = true
463	number of C0 sub C-states using MWAIT = 0x0 (0)
464	number of C1 sub C-states using MWAIT = 0x2 (2)
465	number of C2 sub C-states using MWAIT = 0x1 (1)
466	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
467	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
468	Thermal and Power Management Features (6):
469	digital thermometer = true
470	Intel Turbo Boost Technology = true
471	ARAT always running APIC timer = true
472	PLN power limit notification = true
473	ECMD extended clock modulation duty = true
474	PTM package thermal management = true
475	digital thermometer thresholds = 0x2 (2)
476	ACNT/MCNT supported performance measure = true
477	ACNT2 available = false
478	performance-energy bias capability = true
479	extended feature flags (7):
480	FSGSBASE instructions = true
481	BMI instruction = true
482	SMEP support = true
483	enhanced REP MOVSB/STOSB = true
484	INVPCID instruction = true
485	Direct Cache Access Parameters (9):
486	PLATFORM_DCA_CAP MSR bits = 0
487	Architecture Performance Monitoring Features (0xa/eax):
488	version ID = 0x3 (3)
489	number of counters per logical processor = 0x4 (4)
490	bit width of counter = 0x30 (48)
491	length of EBX bit vector = 0x7 (7)
492	Architecture Performance Monitoring Features (0xa/ebx):
493	core cycle event not available = false
494	instruction retired event not available = false
495	reference cycles event not available = false
496	last-level cache ref event not available = false
497	last-level cache miss event not avail = false
498	branch inst retired event not available = false
499	branch mispred retired event not avail = false
500	Architecture Performance Monitoring Features (0xa/edx):
501	number of fixed counters = 0x3 (3)
502	bit width of fixed counters = 0x30 (48)
503	x2APIC features / processor topology (0xb):
504	--- level 0 (thread) ---
505	bits to shift APIC ID to get next = 0x1 (1)
506	logical processors at this level = 0x2 (2)
507	level number = 0x0 (0)
508	level type = thread (1)
509	extended APIC ID = 2
510	--- level 1 (core) ---
511	bits to shift APIC ID to get next = 0x4 (4)
512	logical processors at this level = 0x8 (8)
513	level number = 0x1 (1)
514	level type = core (2)
515	extended APIC ID = 2
516	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
517	XSAVE features (0xd/0):
518	XCR0 lower 32 bits valid bit field mask = 0x00000007
519	bytes required by fields in XCR0 = 0x00000340 (832)
520	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
521	XCR0 upper 32 bits valid bit field mask = 0x00000000
522	YMM features (0xd/2):
523	YMM save state byte size = 0x00000100 (256)
524	YMM save state byte offset = 0x00000240 (576)
525	LWP features (0xd/0x3e):
526	LWP save state byte size = 0x00000000 (0)
527	LWP save state byte offset = 0x00000000 (0)
528	extended feature flags (0x80000001/edx):
529	SYSCALL and SYSRET instructions = true
530	execution disable = true
531	1-GB large page support = true
532	RDTSCP = true
533	64-bit extensions technology available = true
534	Intel feature flags (0x80000001/ecx):
535	LAHF/SAHF supported in 64-bit mode = true
536	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
537	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
538	instruction # entries = 0x0 (0)
539	instruction associativity = 0x0 (0)
540	data # entries = 0x0 (0)
541	data associativity = 0x0 (0)
542	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
543	instruction # entries = 0x0 (0)
544	instruction associativity = 0x0 (0)
545	data # entries = 0x0 (0)
546	data associativity = 0x0 (0)
547	L1 data cache information (0x80000005/ecx):
548	line size (bytes) = 0x0 (0)
549	lines per tag = 0x0 (0)
550	associativity = 0x0 (0)
551	size (Kb) = 0x0 (0)
552	L1 instruction cache information (0x80000005/edx):
553	line size (bytes) = 0x0 (0)
554	lines per tag = 0x0 (0)
555	associativity = 0x0 (0)
556	size (Kb) = 0x0 (0)
557	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
558	instruction # entries = 0x0 (0)
559	instruction associativity = L2 off (0)
560	data # entries = 0x0 (0)
561	data associativity = L2 off (0)
562	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
563	instruction # entries = 0x0 (0)
564	instruction associativity = L2 off (0)
565	data # entries = 0x0 (0)
566	data associativity = L2 off (0)
567	L2 unified cache information (0x80000006/ecx):
568	line size (bytes) = 0x40 (64)
569	lines per tag = 0x0 (0)
570	associativity = 8-way (6)
571	size (Kb) = 0x100 (256)
572	L3 cache information (0x80000006/edx):
573	line size (bytes) = 0x0 (0)
574	lines per tag = 0x0 (0)
575	associativity = L2 off (0)
576	size (in 512Kb units) = 0x0 (0)
577	Advanced Power Management Features (0x80000007/edx):
578	temperature sensing diode = false
579	frequency ID (FID) control = false
580	voltage ID (VID) control = false
581	thermal trip (TTP) = false
582	thermal monitor (TM) = false
583	software thermal control (STC) = false
584	100 MHz multiplier control = false
585	hardware P-State control = false
586	TscInvariant = true
587	Physical Address and Linear Address Size (0x80000008/eax):
588	maximum physical address bits = 0x27 (39)
589	maximum linear (virtual) address bits = 0x30 (48)
590	maximum guest physical address bits = 0x0 (0)
591	Logical CPU cores (0x80000008/ecx):
592	number of CPU cores - 1 = 0x0 (0)
593	ApicIdCoreIdSize = 0x0 (0)
594	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
595	(multi-processing method): Intel leaf 0xb
596	(APIC widths synth): CORE_width=4 SMT_width=1
597	(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
598	(synth) = Intel Core (unknown model)
599	CPU 2:
600	vendor_id = "GenuineIntel"
601	version information (1/eax):
602	processor type = primary processor (0)
603	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
604	model = 0x6 (6)
605	stepping id = 0x1 (1)
606	extended family = 0x0 (0)
607	extended model = 0x4 (4)
608	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
609	miscellaneous (1/ebx):
610	process local APIC physical ID = 0x4 (4)
611	cpu count = 0x10 (16)
612	CLFLUSH line size = 0x8 (8)
613	brand index = 0x0 (0)
614	brand id = 0x00 (0): unknown
615	feature information (1/edx):
616	x87 FPU on chip = true
617	virtual-8086 mode enhancement = true
618	debugging extensions = true
619	page size extensions = true
620	time stamp counter = true
621	RDMSR and WRMSR support = true
622	physical address extensions = true
623	machine check exception = true
624	CMPXCHG8B inst. = true
625	APIC on chip = true
626	SYSENTER and SYSEXIT = true
627	memory type range registers = true
628	PTE global bit = true
629	machine check architecture = true
630	conditional move/compare instruction = true
631	page attribute table = true
632	page size extension = true
633	processor serial number = false
634	CLFLUSH instruction = true
635	debug store = true
636	thermal monitor and clock ctrl = true
637	MMX Technology = true
638	FXSAVE/FXRSTOR = true
639	SSE extensions = true
640	SSE2 extensions = true
641	self snoop = true
642	hyper-threading / multi-core supported = true
643	therm. monitor = true
644	IA64 = false
645	pending break event = true
646	feature information (1/ecx):
647	PNI/SSE3: Prescott New Instructions = true
648	PCLMULDQ instruction = true
649	64-bit debug store = true
650	MONITOR/MWAIT = true
651	CPL-qualified debug store = true
652	VMX: virtual machine extensions = true
653	SMX: safer mode extensions = false
654	Enhanced Intel SpeedStep Technology = true
655	thermal monitor 2 = true
656	SSSE3 extensions = true
657	context ID: adaptive or shared L1 data = false
658	FMA instruction = true
659	CMPXCHG16B instruction = true
660	xTPR disable = true
661	perfmon and debug = true
662	process context identifiers = true
663	direct cache access = false
664	SSE4.1 extensions = true
665	SSE4.2 extensions = true
666	extended xAPIC support = true
667	MOVBE instruction = true
668	POPCNT instruction = true
669	time stamp counter deadline = true
670	AES instruction = true
671	XSAVE/XSTOR states = true
672	OS-enabled XSAVE/XSTOR = true
673	AVX: advanced vector extensions = true
674	F16C half-precision convert instruction = true
675	RDRAND instruction = true
676	hypervisor guest status = false
677	cache and TLB information (2):
678	0x63: unknown
679	0x03: data TLB: 4K pages, 4-way, 64 entries
680	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
681	0xff: cache data is in CPUID 4
682	0xb5: unknown
683	0xf0: 64 byte prefetching
684	0xc1: unknown
685	processor serial number: 0004-0661-0000-0000-0000-0000
686	deterministic cache parameters (4):
687	--- cache 0 ---
688	cache type = data cache (1)
689	cache level = 0x1 (1)
690	self-initializing cache level = true
691	fully associative cache = false
692	extra threads sharing this cache = 0x1 (1)
693	extra processor cores on this die = 0x7 (7)
694	system coherency line size = 0x3f (63)
695	physical line partitions = 0x0 (0)
696	ways of associativity = 0x7 (7)
697	WBINVD/INVD behavior on lower caches = false
698	inclusive to lower caches = false
699	complex cache indexing = false
700	number of sets - 1 (s) = 63
701	--- cache 1 ---
702	cache type = instruction cache (2)
703	cache level = 0x1 (1)
704	self-initializing cache level = true
705	fully associative cache = false
706	extra threads sharing this cache = 0x1 (1)
707	extra processor cores on this die = 0x7 (7)
708	system coherency line size = 0x3f (63)
709	physical line partitions = 0x0 (0)
710	ways of associativity = 0x7 (7)
711	WBINVD/INVD behavior on lower caches = false
712	inclusive to lower caches = false
713	complex cache indexing = false
714	number of sets - 1 (s) = 63
715	--- cache 2 ---
716	cache type = unified cache (3)
717	cache level = 0x2 (2)
718	self-initializing cache level = true
719	fully associative cache = false
720	extra threads sharing this cache = 0x1 (1)
721	extra processor cores on this die = 0x7 (7)
722	system coherency line size = 0x3f (63)
723	physical line partitions = 0x0 (0)
724	ways of associativity = 0x7 (7)
725	WBINVD/INVD behavior on lower caches = false
726	inclusive to lower caches = false
727	complex cache indexing = false
728	number of sets - 1 (s) = 511
729	--- cache 3 ---
730	cache type = unified cache (3)
731	cache level = 0x3 (3)
732	self-initializing cache level = true
733	fully associative cache = false
734	extra threads sharing this cache = 0xf (15)
735	extra processor cores on this die = 0x7 (7)
736	system coherency line size = 0x3f (63)
737	physical line partitions = 0x0 (0)
738	ways of associativity = 0xb (11)
739	WBINVD/INVD behavior on lower caches = false
740	inclusive to lower caches = true
741	complex cache indexing = true
742	number of sets - 1 (s) = 8191
743	--- cache 4 ---
744	cache type = unified cache (3)
745	cache level = 0x4 (4)
746	self-initializing cache level = true
747	fully associative cache = false
748	extra threads sharing this cache = 0xf (15)
749	extra processor cores on this die = 0x7 (7)
750	system coherency line size = 0x3f (63)
751	physical line partitions = 0xf (15)
752	ways of associativity = 0xf (15)
753	WBINVD/INVD behavior on lower caches = false
754	inclusive to lower caches = false
755	complex cache indexing = true
756	number of sets - 1 (s) = 8191
757	MONITOR/MWAIT (5):
758	smallest monitor-line size (bytes) = 0x40 (64)
759	largest monitor-line size (bytes) = 0x40 (64)
760	enum of Monitor-MWAIT exts supported = true
761	supports intrs as break-event for MWAIT = true
762	number of C0 sub C-states using MWAIT = 0x0 (0)
763	number of C1 sub C-states using MWAIT = 0x2 (2)
764	number of C2 sub C-states using MWAIT = 0x1 (1)
765	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
766	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
767	Thermal and Power Management Features (6):
768	digital thermometer = true
769	Intel Turbo Boost Technology = true
770	ARAT always running APIC timer = true
771	PLN power limit notification = true
772	ECMD extended clock modulation duty = true
773	PTM package thermal management = true
774	digital thermometer thresholds = 0x2 (2)
775	ACNT/MCNT supported performance measure = true
776	ACNT2 available = false
777	performance-energy bias capability = true
778	extended feature flags (7):
779	FSGSBASE instructions = true
780	BMI instruction = true
781	SMEP support = true
782	enhanced REP MOVSB/STOSB = true
783	INVPCID instruction = true
784	Direct Cache Access Parameters (9):
785	PLATFORM_DCA_CAP MSR bits = 0
786	Architecture Performance Monitoring Features (0xa/eax):
787	version ID = 0x3 (3)
788	number of counters per logical processor = 0x4 (4)
789	bit width of counter = 0x30 (48)
790	length of EBX bit vector = 0x7 (7)
791	Architecture Performance Monitoring Features (0xa/ebx):
792	core cycle event not available = false
793	instruction retired event not available = false
794	reference cycles event not available = false
795	last-level cache ref event not available = false
796	last-level cache miss event not avail = false
797	branch inst retired event not available = false
798	branch mispred retired event not avail = false
799	Architecture Performance Monitoring Features (0xa/edx):
800	number of fixed counters = 0x3 (3)
801	bit width of fixed counters = 0x30 (48)
802	x2APIC features / processor topology (0xb):
803	--- level 0 (thread) ---
804	bits to shift APIC ID to get next = 0x1 (1)
805	logical processors at this level = 0x2 (2)
806	level number = 0x0 (0)
807	level type = thread (1)
808	extended APIC ID = 4
809	--- level 1 (core) ---
810	bits to shift APIC ID to get next = 0x4 (4)
811	logical processors at this level = 0x8 (8)
812	level number = 0x1 (1)
813	level type = core (2)
814	extended APIC ID = 4
815	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
816	XSAVE features (0xd/0):
817	XCR0 lower 32 bits valid bit field mask = 0x00000007
818	bytes required by fields in XCR0 = 0x00000340 (832)
819	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
820	XCR0 upper 32 bits valid bit field mask = 0x00000000
821	YMM features (0xd/2):
822	YMM save state byte size = 0x00000100 (256)
823	YMM save state byte offset = 0x00000240 (576)
824	LWP features (0xd/0x3e):
825	LWP save state byte size = 0x00000000 (0)
826	LWP save state byte offset = 0x00000000 (0)
827	extended feature flags (0x80000001/edx):
828	SYSCALL and SYSRET instructions = true
829	execution disable = true
830	1-GB large page support = true
831	RDTSCP = true
832	64-bit extensions technology available = true
833	Intel feature flags (0x80000001/ecx):
834	LAHF/SAHF supported in 64-bit mode = true
835	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
836	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
837	instruction # entries = 0x0 (0)
838	instruction associativity = 0x0 (0)
839	data # entries = 0x0 (0)
840	data associativity = 0x0 (0)
841	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
842	instruction # entries = 0x0 (0)
843	instruction associativity = 0x0 (0)
844	data # entries = 0x0 (0)
845	data associativity = 0x0 (0)
846	L1 data cache information (0x80000005/ecx):
847	line size (bytes) = 0x0 (0)
848	lines per tag = 0x0 (0)
849	associativity = 0x0 (0)
850	size (Kb) = 0x0 (0)
851	L1 instruction cache information (0x80000005/edx):
852	line size (bytes) = 0x0 (0)
853	lines per tag = 0x0 (0)
854	associativity = 0x0 (0)
855	size (Kb) = 0x0 (0)
856	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
857	instruction # entries = 0x0 (0)
858	instruction associativity = L2 off (0)
859	data # entries = 0x0 (0)
860	data associativity = L2 off (0)
861	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
862	instruction # entries = 0x0 (0)
863	instruction associativity = L2 off (0)
864	data # entries = 0x0 (0)
865	data associativity = L2 off (0)
866	L2 unified cache information (0x80000006/ecx):
867	line size (bytes) = 0x40 (64)
868	lines per tag = 0x0 (0)
869	associativity = 8-way (6)
870	size (Kb) = 0x100 (256)
871	L3 cache information (0x80000006/edx):
872	line size (bytes) = 0x0 (0)
873	lines per tag = 0x0 (0)
874	associativity = L2 off (0)
875	size (in 512Kb units) = 0x0 (0)
876	Advanced Power Management Features (0x80000007/edx):
877	temperature sensing diode = false
878	frequency ID (FID) control = false
879	voltage ID (VID) control = false
880	thermal trip (TTP) = false
881	thermal monitor (TM) = false
882	software thermal control (STC) = false
883	100 MHz multiplier control = false
884	hardware P-State control = false
885	TscInvariant = true
886	Physical Address and Linear Address Size (0x80000008/eax):
887	maximum physical address bits = 0x27 (39)
888	maximum linear (virtual) address bits = 0x30 (48)
889	maximum guest physical address bits = 0x0 (0)
890	Logical CPU cores (0x80000008/ecx):
891	number of CPU cores - 1 = 0x0 (0)
892	ApicIdCoreIdSize = 0x0 (0)
893	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
894	(multi-processing method): Intel leaf 0xb
895	(APIC widths synth): CORE_width=4 SMT_width=1
896	(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
897	(synth) = Intel Core (unknown model)
898	CPU 3:
899	vendor_id = "GenuineIntel"
900	version information (1/eax):
901	processor type = primary processor (0)
902	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
903	model = 0x6 (6)
904	stepping id = 0x1 (1)
905	extended family = 0x0 (0)
906	extended model = 0x4 (4)
907	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
908	miscellaneous (1/ebx):
909	process local APIC physical ID = 0x6 (6)
910	cpu count = 0x10 (16)
911	CLFLUSH line size = 0x8 (8)
912	brand index = 0x0 (0)
913	brand id = 0x00 (0): unknown
914	feature information (1/edx):
915	x87 FPU on chip = true
916	virtual-8086 mode enhancement = true
917	debugging extensions = true
918	page size extensions = true
919	time stamp counter = true
920	RDMSR and WRMSR support = true
921	physical address extensions = true
922	machine check exception = true
923	CMPXCHG8B inst. = true
924	APIC on chip = true
925	SYSENTER and SYSEXIT = true
926	memory type range registers = true
927	PTE global bit = true
928	machine check architecture = true
929	conditional move/compare instruction = true
930	page attribute table = true
931	page size extension = true
932	processor serial number = false
933	CLFLUSH instruction = true
934	debug store = true
935	thermal monitor and clock ctrl = true
936	MMX Technology = true
937	FXSAVE/FXRSTOR = true
938	SSE extensions = true
939	SSE2 extensions = true
940	self snoop = true
941	hyper-threading / multi-core supported = true
942	therm. monitor = true
943	IA64 = false
944	pending break event = true
945	feature information (1/ecx):
946	PNI/SSE3: Prescott New Instructions = true
947	PCLMULDQ instruction = true
948	64-bit debug store = true
949	MONITOR/MWAIT = true
950	CPL-qualified debug store = true
951	VMX: virtual machine extensions = true
952	SMX: safer mode extensions = false
953	Enhanced Intel SpeedStep Technology = true
954	thermal monitor 2 = true
955	SSSE3 extensions = true
956	context ID: adaptive or shared L1 data = false
957	FMA instruction = true
958	CMPXCHG16B instruction = true
959	xTPR disable = true
960	perfmon and debug = true
961	process context identifiers = true
962	direct cache access = false
963	SSE4.1 extensions = true
964	SSE4.2 extensions = true
965	extended xAPIC support = true
966	MOVBE instruction = true
967	POPCNT instruction = true
968	time stamp counter deadline = true
969	AES instruction = true
970	XSAVE/XSTOR states = true
971	OS-enabled XSAVE/XSTOR = true
972	AVX: advanced vector extensions = true
973	F16C half-precision convert instruction = true
974	RDRAND instruction = true
975	hypervisor guest status = false
976	cache and TLB information (2):
977	0x63: unknown
978	0x03: data TLB: 4K pages, 4-way, 64 entries
979	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
980	0xff: cache data is in CPUID 4
981	0xb5: unknown
982	0xf0: 64 byte prefetching
983	0xc1: unknown
984	processor serial number: 0004-0661-0000-0000-0000-0000
985	deterministic cache parameters (4):
986	--- cache 0 ---
987	cache type = data cache (1)
988	cache level = 0x1 (1)
989	self-initializing cache level = true
990	fully associative cache = false
991	extra threads sharing this cache = 0x1 (1)
992	extra processor cores on this die = 0x7 (7)
993	system coherency line size = 0x3f (63)
994	physical line partitions = 0x0 (0)
995	ways of associativity = 0x7 (7)
996	WBINVD/INVD behavior on lower caches = false
997	inclusive to lower caches = false
998	complex cache indexing = false
999	number of sets - 1 (s) = 63
1000	--- cache 1 ---
1001	cache type = instruction cache (2)
1002	cache level = 0x1 (1)
1003	self-initializing cache level = true
1004	fully associative cache = false
1005	extra threads sharing this cache = 0x1 (1)
1006	extra processor cores on this die = 0x7 (7)
1007	system coherency line size = 0x3f (63)
1008	physical line partitions = 0x0 (0)
1009	ways of associativity = 0x7 (7)
1010	WBINVD/INVD behavior on lower caches = false
1011	inclusive to lower caches = false
1012	complex cache indexing = false
1013	number of sets - 1 (s) = 63
1014	--- cache 2 ---
1015	cache type = unified cache (3)
1016	cache level = 0x2 (2)
1017	self-initializing cache level = true
1018	fully associative cache = false
1019	extra threads sharing this cache = 0x1 (1)
1020	extra processor cores on this die = 0x7 (7)
1021	system coherency line size = 0x3f (63)
1022	physical line partitions = 0x0 (0)
1023	ways of associativity = 0x7 (7)
1024	WBINVD/INVD behavior on lower caches = false
1025	inclusive to lower caches = false
1026	complex cache indexing = false
1027	number of sets - 1 (s) = 511
1028	--- cache 3 ---
1029	cache type = unified cache (3)
1030	cache level = 0x3 (3)
1031	self-initializing cache level = true
1032	fully associative cache = false
1033	extra threads sharing this cache = 0xf (15)
1034	extra processor cores on this die = 0x7 (7)
1035	system coherency line size = 0x3f (63)
1036	physical line partitions = 0x0 (0)
1037	ways of associativity = 0xb (11)
1038	WBINVD/INVD behavior on lower caches = false
1039	inclusive to lower caches = true
1040	complex cache indexing = true
1041	number of sets - 1 (s) = 8191
1042	--- cache 4 ---
1043	cache type = unified cache (3)
1044	cache level = 0x4 (4)
1045	self-initializing cache level = true
1046	fully associative cache = false
1047	extra threads sharing this cache = 0xf (15)
1048	extra processor cores on this die = 0x7 (7)
1049	system coherency line size = 0x3f (63)
1050	physical line partitions = 0xf (15)
1051	ways of associativity = 0xf (15)
1052	WBINVD/INVD behavior on lower caches = false
1053	inclusive to lower caches = false
1054	complex cache indexing = true
1055	number of sets - 1 (s) = 8191
1056	MONITOR/MWAIT (5):
1057	smallest monitor-line size (bytes) = 0x40 (64)
1058	largest monitor-line size (bytes) = 0x40 (64)
1059	enum of Monitor-MWAIT exts supported = true
1060	supports intrs as break-event for MWAIT = true
1061	number of C0 sub C-states using MWAIT = 0x0 (0)
1062	number of C1 sub C-states using MWAIT = 0x2 (2)
1063	number of C2 sub C-states using MWAIT = 0x1 (1)
1064	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
1065	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
1066	Thermal and Power Management Features (6):
1067	digital thermometer = true
1068	Intel Turbo Boost Technology = true
1069	ARAT always running APIC timer = true
1070	PLN power limit notification = true
1071	ECMD extended clock modulation duty = true
1072	PTM package thermal management = true
1073	digital thermometer thresholds = 0x2 (2)
1074	ACNT/MCNT supported performance measure = true
1075	ACNT2 available = false
1076	performance-energy bias capability = true
1077	extended feature flags (7):
1078	FSGSBASE instructions = true
1079	BMI instruction = true
1080	SMEP support = true
1081	enhanced REP MOVSB/STOSB = true
1082	INVPCID instruction = true
1083	Direct Cache Access Parameters (9):
1084	PLATFORM_DCA_CAP MSR bits = 0
1085	Architecture Performance Monitoring Features (0xa/eax):
1086	version ID = 0x3 (3)
1087	number of counters per logical processor = 0x4 (4)
1088	bit width of counter = 0x30 (48)
1089	length of EBX bit vector = 0x7 (7)
1090	Architecture Performance Monitoring Features (0xa/ebx):
1091	core cycle event not available = false
1092	instruction retired event not available = false
1093	reference cycles event not available = false
1094	last-level cache ref event not available = false
1095	last-level cache miss event not avail = false
1096	branch inst retired event not available = false
1097	branch mispred retired event not avail = false
1098	Architecture Performance Monitoring Features (0xa/edx):
1099	number of fixed counters = 0x3 (3)
1100	bit width of fixed counters = 0x30 (48)
1101	x2APIC features / processor topology (0xb):
1102	--- level 0 (thread) ---
1103	bits to shift APIC ID to get next = 0x1 (1)
1104	logical processors at this level = 0x2 (2)
1105	level number = 0x0 (0)
1106	level type = thread (1)
1107	extended APIC ID = 6
1108	--- level 1 (core) ---
1109	bits to shift APIC ID to get next = 0x4 (4)
1110	logical processors at this level = 0x8 (8)
1111	level number = 0x1 (1)
1112	level type = core (2)
1113	extended APIC ID = 6
1114	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
1115	XSAVE features (0xd/0):
1116	XCR0 lower 32 bits valid bit field mask = 0x00000007
1117	bytes required by fields in XCR0 = 0x00000340 (832)
1118	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
1119	XCR0 upper 32 bits valid bit field mask = 0x00000000
1120	YMM features (0xd/2):
1121	YMM save state byte size = 0x00000100 (256)
1122	YMM save state byte offset = 0x00000240 (576)
1123	LWP features (0xd/0x3e):
1124	LWP save state byte size = 0x00000000 (0)
1125	LWP save state byte offset = 0x00000000 (0)
1126	extended feature flags (0x80000001/edx):
1127	SYSCALL and SYSRET instructions = true
1128	execution disable = true
1129	1-GB large page support = true
1130	RDTSCP = true
1131	64-bit extensions technology available = true
1132	Intel feature flags (0x80000001/ecx):
1133	LAHF/SAHF supported in 64-bit mode = true
1134	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
1135	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
1136	instruction # entries = 0x0 (0)
1137	instruction associativity = 0x0 (0)
1138	data # entries = 0x0 (0)
1139	data associativity = 0x0 (0)
1140	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
1141	instruction # entries = 0x0 (0)
1142	instruction associativity = 0x0 (0)
1143	data # entries = 0x0 (0)
1144	data associativity = 0x0 (0)
1145	L1 data cache information (0x80000005/ecx):
1146	line size (bytes) = 0x0 (0)
1147	lines per tag = 0x0 (0)
1148	associativity = 0x0 (0)
1149	size (Kb) = 0x0 (0)
1150	L1 instruction cache information (0x80000005/edx):
1151	line size (bytes) = 0x0 (0)
1152	lines per tag = 0x0 (0)
1153	associativity = 0x0 (0)
1154	size (Kb) = 0x0 (0)
1155	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
1156	instruction # entries = 0x0 (0)
1157	instruction associativity = L2 off (0)
1158	data # entries = 0x0 (0)
1159	data associativity = L2 off (0)
1160	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
1161	instruction # entries = 0x0 (0)
1162	instruction associativity = L2 off (0)
1163	data # entries = 0x0 (0)
1164	data associativity = L2 off (0)
1165	L2 unified cache information (0x80000006/ecx):
1166	line size (bytes) = 0x40 (64)
1167	lines per tag = 0x0 (0)
1168	associativity = 8-way (6)
1169	size (Kb) = 0x100 (256)
1170	L3 cache information (0x80000006/edx):
1171	line size (bytes) = 0x0 (0)
1172	lines per tag = 0x0 (0)
1173	associativity = L2 off (0)
1174	size (in 512Kb units) = 0x0 (0)
1175	Advanced Power Management Features (0x80000007/edx):
1176	temperature sensing diode = false
1177	frequency ID (FID) control = false
1178	voltage ID (VID) control = false
1179	thermal trip (TTP) = false
1180	thermal monitor (TM) = false
1181	software thermal control (STC) = false
1182	100 MHz multiplier control = false
1183	hardware P-State control = false
1184	TscInvariant = true
1185	Physical Address and Linear Address Size (0x80000008/eax):
1186	maximum physical address bits = 0x27 (39)
1187	maximum linear (virtual) address bits = 0x30 (48)
1188	maximum guest physical address bits = 0x0 (0)
1189	Logical CPU cores (0x80000008/ecx):
1190	number of CPU cores - 1 = 0x0 (0)
1191	ApicIdCoreIdSize = 0x0 (0)
1192	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
1193	(multi-processing method): Intel leaf 0xb
1194	(APIC widths synth): CORE_width=4 SMT_width=1
1195	(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
1196	(synth) = Intel Core (unknown model)
1197	CPU 4:
1198	vendor_id = "GenuineIntel"
1199	version information (1/eax):
1200	processor type = primary processor (0)
1201	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
1202	model = 0x6 (6)
1203	stepping id = 0x1 (1)
1204	extended family = 0x0 (0)
1205	extended model = 0x4 (4)
1206	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
1207	miscellaneous (1/ebx):
1208	process local APIC physical ID = 0x1 (1)
1209	cpu count = 0x10 (16)
1210	CLFLUSH line size = 0x8 (8)
1211	brand index = 0x0 (0)
1212	brand id = 0x00 (0): unknown
1213	feature information (1/edx):
1214	x87 FPU on chip = true
1215	virtual-8086 mode enhancement = true
1216	debugging extensions = true
1217	page size extensions = true
1218	time stamp counter = true
1219	RDMSR and WRMSR support = true
1220	physical address extensions = true
1221	machine check exception = true
1222	CMPXCHG8B inst. = true
1223	APIC on chip = true
1224	SYSENTER and SYSEXIT = true
1225	memory type range registers = true
1226	PTE global bit = true
1227	machine check architecture = true
1228	conditional move/compare instruction = true
1229	page attribute table = true
1230	page size extension = true
1231	processor serial number = false
1232	CLFLUSH instruction = true
1233	debug store = true
1234	thermal monitor and clock ctrl = true
1235	MMX Technology = true
1236	FXSAVE/FXRSTOR = true
1237	SSE extensions = true
1238	SSE2 extensions = true
1239	self snoop = true
1240	hyper-threading / multi-core supported = true
1241	therm. monitor = true
1242	IA64 = false
1243	pending break event = true
1244	feature information (1/ecx):
1245	PNI/SSE3: Prescott New Instructions = true
1246	PCLMULDQ instruction = true
1247	64-bit debug store = true
1248	MONITOR/MWAIT = true
1249	CPL-qualified debug store = true
1250	VMX: virtual machine extensions = true
1251	SMX: safer mode extensions = false
1252	Enhanced Intel SpeedStep Technology = true
1253	thermal monitor 2 = true
1254	SSSE3 extensions = true
1255	context ID: adaptive or shared L1 data = false
1256	FMA instruction = true
1257	CMPXCHG16B instruction = true
1258	xTPR disable = true
1259	perfmon and debug = true
1260	process context identifiers = true
1261	direct cache access = false
1262	SSE4.1 extensions = true
1263	SSE4.2 extensions = true
1264	extended xAPIC support = true
1265	MOVBE instruction = true
1266	POPCNT instruction = true
1267	time stamp counter deadline = true
1268	AES instruction = true
1269	XSAVE/XSTOR states = true
1270	OS-enabled XSAVE/XSTOR = true
1271	AVX: advanced vector extensions = true
1272	F16C half-precision convert instruction = true
1273	RDRAND instruction = true
1274	hypervisor guest status = false
1275	cache and TLB information (2):
1276	0x63: unknown
1277	0x03: data TLB: 4K pages, 4-way, 64 entries
1278	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
1279	0xff: cache data is in CPUID 4
1280	0xb5: unknown
1281	0xf0: 64 byte prefetching
1282	0xc1: unknown
1283	processor serial number: 0004-0661-0000-0000-0000-0000
1284	deterministic cache parameters (4):
1285	--- cache 0 ---
1286	cache type = data cache (1)
1287	cache level = 0x1 (1)
1288	self-initializing cache level = true
1289	fully associative cache = false
1290	extra threads sharing this cache = 0x1 (1)
1291	extra processor cores on this die = 0x7 (7)
1292	system coherency line size = 0x3f (63)
1293	physical line partitions = 0x0 (0)
1294	ways of associativity = 0x7 (7)
1295	WBINVD/INVD behavior on lower caches = false
1296	inclusive to lower caches = false
1297	complex cache indexing = false
1298	number of sets - 1 (s) = 63
1299	--- cache 1 ---
1300	cache type = instruction cache (2)
1301	cache level = 0x1 (1)
1302	self-initializing cache level = true
1303	fully associative cache = false
1304	extra threads sharing this cache = 0x1 (1)
1305	extra processor cores on this die = 0x7 (7)
1306	system coherency line size = 0x3f (63)
1307	physical line partitions = 0x0 (0)
1308	ways of associativity = 0x7 (7)
1309	WBINVD/INVD behavior on lower caches = false
1310	inclusive to lower caches = false
1311	complex cache indexing = false
1312	number of sets - 1 (s) = 63
1313	--- cache 2 ---
1314	cache type = unified cache (3)
1315	cache level = 0x2 (2)
1316	self-initializing cache level = true
1317	fully associative cache = false
1318	extra threads sharing this cache = 0x1 (1)
1319	extra processor cores on this die = 0x7 (7)
1320	system coherency line size = 0x3f (63)
1321	physical line partitions = 0x0 (0)
1322	ways of associativity = 0x7 (7)
1323	WBINVD/INVD behavior on lower caches = false
1324	inclusive to lower caches = false
1325	complex cache indexing = false
1326	number of sets - 1 (s) = 511
1327	--- cache 3 ---
1328	cache type = unified cache (3)
1329	cache level = 0x3 (3)
1330	self-initializing cache level = true
1331	fully associative cache = false
1332	extra threads sharing this cache = 0xf (15)
1333	extra processor cores on this die = 0x7 (7)
1334	system coherency line size = 0x3f (63)
1335	physical line partitions = 0x0 (0)
1336	ways of associativity = 0xb (11)
1337	WBINVD/INVD behavior on lower caches = false
1338	inclusive to lower caches = true
1339	complex cache indexing = true
1340	number of sets - 1 (s) = 8191
1341	--- cache 4 ---
1342	cache type = unified cache (3)
1343	cache level = 0x4 (4)
1344	self-initializing cache level = true
1345	fully associative cache = false
1346	extra threads sharing this cache = 0xf (15)
1347	extra processor cores on this die = 0x7 (7)
1348	system coherency line size = 0x3f (63)
1349	physical line partitions = 0xf (15)
1350	ways of associativity = 0xf (15)
1351	WBINVD/INVD behavior on lower caches = false
1352	inclusive to lower caches = false
1353	complex cache indexing = true
1354	number of sets - 1 (s) = 8191
1355	MONITOR/MWAIT (5):
1356	smallest monitor-line size (bytes) = 0x40 (64)
1357	largest monitor-line size (bytes) = 0x40 (64)
1358	enum of Monitor-MWAIT exts supported = true
1359	supports intrs as break-event for MWAIT = true
1360	number of C0 sub C-states using MWAIT = 0x0 (0)
1361	number of C1 sub C-states using MWAIT = 0x2 (2)
1362	number of C2 sub C-states using MWAIT = 0x1 (1)
1363	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
1364	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
1365	Thermal and Power Management Features (6):
1366	digital thermometer = true
1367	Intel Turbo Boost Technology = true
1368	ARAT always running APIC timer = true
1369	PLN power limit notification = true
1370	ECMD extended clock modulation duty = true
1371	PTM package thermal management = true
1372	digital thermometer thresholds = 0x2 (2)
1373	ACNT/MCNT supported performance measure = true
1374	ACNT2 available = false
1375	performance-energy bias capability = true
1376	extended feature flags (7):
1377	FSGSBASE instructions = true
1378	BMI instruction = true
1379	SMEP support = true
1380	enhanced REP MOVSB/STOSB = true
1381	INVPCID instruction = true
1382	Direct Cache Access Parameters (9):
1383	PLATFORM_DCA_CAP MSR bits = 0
1384	Architecture Performance Monitoring Features (0xa/eax):
1385	version ID = 0x3 (3)
1386	number of counters per logical processor = 0x4 (4)
1387	bit width of counter = 0x30 (48)
1388	length of EBX bit vector = 0x7 (7)
1389	Architecture Performance Monitoring Features (0xa/ebx):
1390	core cycle event not available = false
1391	instruction retired event not available = false
1392	reference cycles event not available = false
1393	last-level cache ref event not available = false
1394	last-level cache miss event not avail = false
1395	branch inst retired event not available = false
1396	branch mispred retired event not avail = false
1397	Architecture Performance Monitoring Features (0xa/edx):
1398	number of fixed counters = 0x3 (3)
1399	bit width of fixed counters = 0x30 (48)
1400	x2APIC features / processor topology (0xb):
1401	--- level 0 (thread) ---
1402	bits to shift APIC ID to get next = 0x1 (1)
1403	logical processors at this level = 0x2 (2)
1404	level number = 0x0 (0)
1405	level type = thread (1)
1406	extended APIC ID = 1
1407	--- level 1 (core) ---
1408	bits to shift APIC ID to get next = 0x4 (4)
1409	logical processors at this level = 0x8 (8)
1410	level number = 0x1 (1)
1411	level type = core (2)
1412	extended APIC ID = 1
1413	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
1414	XSAVE features (0xd/0):
1415	XCR0 lower 32 bits valid bit field mask = 0x00000007
1416	bytes required by fields in XCR0 = 0x00000340 (832)
1417	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
1418	XCR0 upper 32 bits valid bit field mask = 0x00000000
1419	YMM features (0xd/2):
1420	YMM save state byte size = 0x00000100 (256)
1421	YMM save state byte offset = 0x00000240 (576)
1422	LWP features (0xd/0x3e):
1423	LWP save state byte size = 0x00000000 (0)
1424	LWP save state byte offset = 0x00000000 (0)
1425	extended feature flags (0x80000001/edx):
1426	SYSCALL and SYSRET instructions = true
1427	execution disable = true
1428	1-GB large page support = true
1429	RDTSCP = true
1430	64-bit extensions technology available = true
1431	Intel feature flags (0x80000001/ecx):
1432	LAHF/SAHF supported in 64-bit mode = true
1433	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
1434	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
1435	instruction # entries = 0x0 (0)
1436	instruction associativity = 0x0 (0)
1437	data # entries = 0x0 (0)
1438	data associativity = 0x0 (0)
1439	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
1440	instruction # entries = 0x0 (0)
1441	instruction associativity = 0x0 (0)
1442	data # entries = 0x0 (0)
1443	data associativity = 0x0 (0)
1444	L1 data cache information (0x80000005/ecx):
1445	line size (bytes) = 0x0 (0)
1446	lines per tag = 0x0 (0)
1447	associativity = 0x0 (0)
1448	size (Kb) = 0x0 (0)
1449	L1 instruction cache information (0x80000005/edx):
1450	line size (bytes) = 0x0 (0)
1451	lines per tag = 0x0 (0)
1452	associativity = 0x0 (0)
1453	size (Kb) = 0x0 (0)
1454	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
1455	instruction # entries = 0x0 (0)
1456	instruction associativity = L2 off (0)
1457	data # entries = 0x0 (0)
1458	data associativity = L2 off (0)
1459	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
1460	instruction # entries = 0x0 (0)
1461	instruction associativity = L2 off (0)
1462	data # entries = 0x0 (0)
1463	data associativity = L2 off (0)
1464	L2 unified cache information (0x80000006/ecx):
1465	line size (bytes) = 0x40 (64)
1466	lines per tag = 0x0 (0)
1467	associativity = 8-way (6)
1468	size (Kb) = 0x100 (256)
1469	L3 cache information (0x80000006/edx):
1470	line size (bytes) = 0x0 (0)
1471	lines per tag = 0x0 (0)
1472	associativity = L2 off (0)
1473	size (in 512Kb units) = 0x0 (0)
1474	Advanced Power Management Features (0x80000007/edx):
1475	temperature sensing diode = false
1476	frequency ID (FID) control = false
1477	voltage ID (VID) control = false
1478	thermal trip (TTP) = false
1479	thermal monitor (TM) = false
1480	software thermal control (STC) = false
1481	100 MHz multiplier control = false
1482	hardware P-State control = false
1483	TscInvariant = true
1484	Physical Address and Linear Address Size (0x80000008/eax):
1485	maximum physical address bits = 0x27 (39)
1486	maximum linear (virtual) address bits = 0x30 (48)
1487	maximum guest physical address bits = 0x0 (0)
1488	Logical CPU cores (0x80000008/ecx):
1489	number of CPU cores - 1 = 0x0 (0)
1490	ApicIdCoreIdSize = 0x0 (0)
1491	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
1492	(multi-processing method): Intel leaf 0xb
1493	(APIC widths synth): CORE_width=4 SMT_width=1
1494	(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
1495	(synth) = Intel Core (unknown model)
1496	CPU 5:
1497	vendor_id = "GenuineIntel"
1498	version information (1/eax):
1499	processor type = primary processor (0)
1500	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
1501	model = 0x6 (6)
1502	stepping id = 0x1 (1)
1503	extended family = 0x0 (0)
1504	extended model = 0x4 (4)
1505	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
1506	miscellaneous (1/ebx):
1507	process local APIC physical ID = 0x3 (3)
1508	cpu count = 0x10 (16)
1509	CLFLUSH line size = 0x8 (8)
1510	brand index = 0x0 (0)
1511	brand id = 0x00 (0): unknown
1512	feature information (1/edx):
1513	x87 FPU on chip = true
1514	virtual-8086 mode enhancement = true
1515	debugging extensions = true
1516	page size extensions = true
1517	time stamp counter = true
1518	RDMSR and WRMSR support = true
1519	physical address extensions = true
1520	machine check exception = true
1521	CMPXCHG8B inst. = true
1522	APIC on chip = true
1523	SYSENTER and SYSEXIT = true
1524	memory type range registers = true
1525	PTE global bit = true
1526	machine check architecture = true
1527	conditional move/compare instruction = true
1528	page attribute table = true
1529	page size extension = true
1530	processor serial number = false
1531	CLFLUSH instruction = true
1532	debug store = true
1533	thermal monitor and clock ctrl = true
1534	MMX Technology = true
1535	FXSAVE/FXRSTOR = true
1536	SSE extensions = true
1537	SSE2 extensions = true
1538	self snoop = true
1539	hyper-threading / multi-core supported = true
1540	therm. monitor = true
1541	IA64 = false
1542	pending break event = true
1543	feature information (1/ecx):
1544	PNI/SSE3: Prescott New Instructions = true
1545	PCLMULDQ instruction = true
1546	64-bit debug store = true
1547	MONITOR/MWAIT = true
1548	CPL-qualified debug store = true
1549	VMX: virtual machine extensions = true
1550	SMX: safer mode extensions = false
1551	Enhanced Intel SpeedStep Technology = true
1552	thermal monitor 2 = true
1553	SSSE3 extensions = true
1554	context ID: adaptive or shared L1 data = false
1555	FMA instruction = true
1556	CMPXCHG16B instruction = true
1557	xTPR disable = true
1558	perfmon and debug = true
1559	process context identifiers = true
1560	direct cache access = false
1561	SSE4.1 extensions = true
1562	SSE4.2 extensions = true
1563	extended xAPIC support = true
1564	MOVBE instruction = true
1565	POPCNT instruction = true
1566	time stamp counter deadline = true
1567	AES instruction = true
1568	XSAVE/XSTOR states = true
1569	OS-enabled XSAVE/XSTOR = true
1570	AVX: advanced vector extensions = true
1571	F16C half-precision convert instruction = true
1572	RDRAND instruction = true
1573	hypervisor guest status = false
1574	cache and TLB information (2):
1575	0x63: unknown
1576	0x03: data TLB: 4K pages, 4-way, 64 entries
1577	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
1578	0xff: cache data is in CPUID 4
1579	0xb5: unknown
1580	0xf0: 64 byte prefetching
1581	0xc1: unknown
1582	processor serial number: 0004-0661-0000-0000-0000-0000
1583	deterministic cache parameters (4):
1584	--- cache 0 ---
1585	cache type = data cache (1)
1586	cache level = 0x1 (1)
1587	self-initializing cache level = true
1588	fully associative cache = false
1589	extra threads sharing this cache = 0x1 (1)
1590	extra processor cores on this die = 0x7 (7)
1591	system coherency line size = 0x3f (63)
1592	physical line partitions = 0x0 (0)
1593	ways of associativity = 0x7 (7)
1594	WBINVD/INVD behavior on lower caches = false
1595	inclusive to lower caches = false
1596	complex cache indexing = false
1597	number of sets - 1 (s) = 63
1598	--- cache 1 ---
1599	cache type = instruction cache (2)
1600	cache level = 0x1 (1)
1601	self-initializing cache level = true
1602	fully associative cache = false
1603	extra threads sharing this cache = 0x1 (1)
1604	extra processor cores on this die = 0x7 (7)
1605	system coherency line size = 0x3f (63)
1606	physical line partitions = 0x0 (0)
1607	ways of associativity = 0x7 (7)
1608	WBINVD/INVD behavior on lower caches = false
1609	inclusive to lower caches = false
1610	complex cache indexing = false
1611	number of sets - 1 (s) = 63
1612	--- cache 2 ---
1613	cache type = unified cache (3)
1614	cache level = 0x2 (2)
1615	self-initializing cache level = true
1616	fully associative cache = false
1617	extra threads sharing this cache = 0x1 (1)
1618	extra processor cores on this die = 0x7 (7)
1619	system coherency line size = 0x3f (63)
1620	physical line partitions = 0x0 (0)
1621	ways of associativity = 0x7 (7)
1622	WBINVD/INVD behavior on lower caches = false
1623	inclusive to lower caches = false
1624	complex cache indexing = false
1625	number of sets - 1 (s) = 511
1626	--- cache 3 ---
1627	cache type = unified cache (3)
1628	cache level = 0x3 (3)
1629	self-initializing cache level = true
1630	fully associative cache = false
1631	extra threads sharing this cache = 0xf (15)
1632	extra processor cores on this die = 0x7 (7)
1633	system coherency line size = 0x3f (63)
1634	physical line partitions = 0x0 (0)
1635	ways of associativity = 0xb (11)
1636	WBINVD/INVD behavior on lower caches = false
1637	inclusive to lower caches = true
1638	complex cache indexing = true
1639	number of sets - 1 (s) = 8191
1640	--- cache 4 ---
1641	cache type = unified cache (3)
1642	cache level = 0x4 (4)
1643	self-initializing cache level = true
1644	fully associative cache = false
1645	extra threads sharing this cache = 0xf (15)
1646	extra processor cores on this die = 0x7 (7)
1647	system coherency line size = 0x3f (63)
1648	physical line partitions = 0xf (15)
1649	ways of associativity = 0xf (15)
1650	WBINVD/INVD behavior on lower caches = false
1651	inclusive to lower caches = false
1652	complex cache indexing = true
1653	number of sets - 1 (s) = 8191
1654	MONITOR/MWAIT (5):
1655	smallest monitor-line size (bytes) = 0x40 (64)
1656	largest monitor-line size (bytes) = 0x40 (64)
1657	enum of Monitor-MWAIT exts supported = true
1658	supports intrs as break-event for MWAIT = true
1659	number of C0 sub C-states using MWAIT = 0x0 (0)
1660	number of C1 sub C-states using MWAIT = 0x2 (2)
1661	number of C2 sub C-states using MWAIT = 0x1 (1)
1662	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
1663	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
1664	Thermal and Power Management Features (6):
1665	digital thermometer = true
1666	Intel Turbo Boost Technology = true
1667	ARAT always running APIC timer = true
1668	PLN power limit notification = true
1669	ECMD extended clock modulation duty = true
1670	PTM package thermal management = true
1671	digital thermometer thresholds = 0x2 (2)
1672	ACNT/MCNT supported performance measure = true
1673	ACNT2 available = false
1674	performance-energy bias capability = true
1675	extended feature flags (7):
1676	FSGSBASE instructions = true
1677	BMI instruction = true
1678	SMEP support = true
1679	enhanced REP MOVSB/STOSB = true
1680	INVPCID instruction = true
1681	Direct Cache Access Parameters (9):
1682	PLATFORM_DCA_CAP MSR bits = 0
1683	Architecture Performance Monitoring Features (0xa/eax):
1684	version ID = 0x3 (3)
1685	number of counters per logical processor = 0x4 (4)
1686	bit width of counter = 0x30 (48)
1687	length of EBX bit vector = 0x7 (7)
1688	Architecture Performance Monitoring Features (0xa/ebx):
1689	core cycle event not available = false
1690	instruction retired event not available = false
1691	reference cycles event not available = false
1692	last-level cache ref event not available = false
1693	last-level cache miss event not avail = false
1694	branch inst retired event not available = false
1695	branch mispred retired event not avail = false
1696	Architecture Performance Monitoring Features (0xa/edx):
1697	number of fixed counters = 0x3 (3)
1698	bit width of fixed counters = 0x30 (48)
1699	x2APIC features / processor topology (0xb):
1700	--- level 0 (thread) ---
1701	bits to shift APIC ID to get next = 0x1 (1)
1702	logical processors at this level = 0x2 (2)
1703	level number = 0x0 (0)
1704	level type = thread (1)
1705	extended APIC ID = 3
1706	--- level 1 (core) ---
1707	bits to shift APIC ID to get next = 0x4 (4)
1708	logical processors at this level = 0x8 (8)
1709	level number = 0x1 (1)
1710	level type = core (2)
1711	extended APIC ID = 3
1712	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
1713	XSAVE features (0xd/0):
1714	XCR0 lower 32 bits valid bit field mask = 0x00000007
1715	bytes required by fields in XCR0 = 0x00000340 (832)
1716	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
1717	XCR0 upper 32 bits valid bit field mask = 0x00000000
1718	YMM features (0xd/2):
1719	YMM save state byte size = 0x00000100 (256)
1720	YMM save state byte offset = 0x00000240 (576)
1721	LWP features (0xd/0x3e):
1722	LWP save state byte size = 0x00000000 (0)
1723	LWP save state byte offset = 0x00000000 (0)
1724	extended feature flags (0x80000001/edx):
1725	SYSCALL and SYSRET instructions = true
1726	execution disable = true
1727	1-GB large page support = true
1728	RDTSCP = true
1729	64-bit extensions technology available = true
1730	Intel feature flags (0x80000001/ecx):
1731	LAHF/SAHF supported in 64-bit mode = true
1732	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
1733	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
1734	instruction # entries = 0x0 (0)
1735	instruction associativity = 0x0 (0)
1736	data # entries = 0x0 (0)
1737	data associativity = 0x0 (0)
1738	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
1739	instruction # entries = 0x0 (0)
1740	instruction associativity = 0x0 (0)
1741	data # entries = 0x0 (0)
1742	data associativity = 0x0 (0)
1743	L1 data cache information (0x80000005/ecx):
1744	line size (bytes) = 0x0 (0)
1745	lines per tag = 0x0 (0)
1746	associativity = 0x0 (0)
1747	size (Kb) = 0x0 (0)
1748	L1 instruction cache information (0x80000005/edx):
1749	line size (bytes) = 0x0 (0)
1750	lines per tag = 0x0 (0)
1751	associativity = 0x0 (0)
1752	size (Kb) = 0x0 (0)
1753	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
1754	instruction # entries = 0x0 (0)
1755	instruction associativity = L2 off (0)
1756	data # entries = 0x0 (0)
1757	data associativity = L2 off (0)
1758	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
1759	instruction # entries = 0x0 (0)
1760	instruction associativity = L2 off (0)
1761	data # entries = 0x0 (0)
1762	data associativity = L2 off (0)
1763	L2 unified cache information (0x80000006/ecx):
1764	line size (bytes) = 0x40 (64)
1765	lines per tag = 0x0 (0)
1766	associativity = 8-way (6)
1767	size (Kb) = 0x100 (256)
1768	L3 cache information (0x80000006/edx):
1769	line size (bytes) = 0x0 (0)
1770	lines per tag = 0x0 (0)
1771	associativity = L2 off (0)
1772	size (in 512Kb units) = 0x0 (0)
1773	Advanced Power Management Features (0x80000007/edx):
1774	temperature sensing diode = false
1775	frequency ID (FID) control = false
1776	voltage ID (VID) control = false
1777	thermal trip (TTP) = false
1778	thermal monitor (TM) = false
1779	software thermal control (STC) = false
1780	100 MHz multiplier control = false
1781	hardware P-State control = false
1782	TscInvariant = true
1783	Physical Address and Linear Address Size (0x80000008/eax):
1784	maximum physical address bits = 0x27 (39)
1785	maximum linear (virtual) address bits = 0x30 (48)
1786	maximum guest physical address bits = 0x0 (0)
1787	Logical CPU cores (0x80000008/ecx):
1788	number of CPU cores - 1 = 0x0 (0)
1789	ApicIdCoreIdSize = 0x0 (0)
1790	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
1791	(multi-processing method): Intel leaf 0xb
1792	(APIC widths synth): CORE_width=4 SMT_width=1
1793	(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
1794	(synth) = Intel Core (unknown model)
1795	CPU 6:
1796	vendor_id = "GenuineIntel"
1797	version information (1/eax):
1798	processor type = primary processor (0)
1799	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
1800	model = 0x6 (6)
1801	stepping id = 0x1 (1)
1802	extended family = 0x0 (0)
1803	extended model = 0x4 (4)
1804	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
1805	miscellaneous (1/ebx):
1806	process local APIC physical ID = 0x5 (5)
1807	cpu count = 0x10 (16)
1808	CLFLUSH line size = 0x8 (8)
1809	brand index = 0x0 (0)
1810	brand id = 0x00 (0): unknown
1811	feature information (1/edx):
1812	x87 FPU on chip = true
1813	virtual-8086 mode enhancement = true
1814	debugging extensions = true
1815	page size extensions = true
1816	time stamp counter = true
1817	RDMSR and WRMSR support = true
1818	physical address extensions = true
1819	machine check exception = true
1820	CMPXCHG8B inst. = true
1821	APIC on chip = true
1822	SYSENTER and SYSEXIT = true
1823	memory type range registers = true
1824	PTE global bit = true
1825	machine check architecture = true
1826	conditional move/compare instruction = true
1827	page attribute table = true
1828	page size extension = true
1829	processor serial number = false
1830	CLFLUSH instruction = true
1831	debug store = true
1832	thermal monitor and clock ctrl = true
1833	MMX Technology = true
1834	FXSAVE/FXRSTOR = true
1835	SSE extensions = true
1836	SSE2 extensions = true
1837	self snoop = true
1838	hyper-threading / multi-core supported = true
1839	therm. monitor = true
1840	IA64 = false
1841	pending break event = true
1842	feature information (1/ecx):
1843	PNI/SSE3: Prescott New Instructions = true
1844	PCLMULDQ instruction = true
1845	64-bit debug store = true
1846	MONITOR/MWAIT = true
1847	CPL-qualified debug store = true
1848	VMX: virtual machine extensions = true
1849	SMX: safer mode extensions = false
1850	Enhanced Intel SpeedStep Technology = true
1851	thermal monitor 2 = true
1852	SSSE3 extensions = true
1853	context ID: adaptive or shared L1 data = false
1854	FMA instruction = true
1855	CMPXCHG16B instruction = true
1856	xTPR disable = true
1857	perfmon and debug = true
1858	process context identifiers = true
1859	direct cache access = false
1860	SSE4.1 extensions = true
1861	SSE4.2 extensions = true
1862	extended xAPIC support = true
1863	MOVBE instruction = true
1864	POPCNT instruction = true
1865	time stamp counter deadline = true
1866	AES instruction = true
1867	XSAVE/XSTOR states = true
1868	OS-enabled XSAVE/XSTOR = true
1869	AVX: advanced vector extensions = true
1870	F16C half-precision convert instruction = true
1871	RDRAND instruction = true
1872	hypervisor guest status = false
1873	cache and TLB information (2):
1874	0x63: unknown
1875	0x03: data TLB: 4K pages, 4-way, 64 entries
1876	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
1877	0xff: cache data is in CPUID 4
1878	0xb5: unknown
1879	0xf0: 64 byte prefetching
1880	0xc1: unknown
1881	processor serial number: 0004-0661-0000-0000-0000-0000
1882	deterministic cache parameters (4):
1883	--- cache 0 ---
1884	cache type = data cache (1)
1885	cache level = 0x1 (1)
1886	self-initializing cache level = true
1887	fully associative cache = false
1888	extra threads sharing this cache = 0x1 (1)
1889	extra processor cores on this die = 0x7 (7)
1890	system coherency line size = 0x3f (63)
1891	physical line partitions = 0x0 (0)
1892	ways of associativity = 0x7 (7)
1893	WBINVD/INVD behavior on lower caches = false
1894	inclusive to lower caches = false
1895	complex cache indexing = false
1896	number of sets - 1 (s) = 63
1897	--- cache 1 ---
1898	cache type = instruction cache (2)
1899	cache level = 0x1 (1)
1900	self-initializing cache level = true
1901	fully associative cache = false
1902	extra threads sharing this cache = 0x1 (1)
1903	extra processor cores on this die = 0x7 (7)
1904	system coherency line size = 0x3f (63)
1905	physical line partitions = 0x0 (0)
1906	ways of associativity = 0x7 (7)
1907	WBINVD/INVD behavior on lower caches = false
1908	inclusive to lower caches = false
1909	complex cache indexing = false
1910	number of sets - 1 (s) = 63
1911	--- cache 2 ---
1912	cache type = unified cache (3)
1913	cache level = 0x2 (2)
1914	self-initializing cache level = true
1915	fully associative cache = false
1916	extra threads sharing this cache = 0x1 (1)
1917	extra processor cores on this die = 0x7 (7)
1918	system coherency line size = 0x3f (63)
1919	physical line partitions = 0x0 (0)
1920	ways of associativity = 0x7 (7)
1921	WBINVD/INVD behavior on lower caches = false
1922	inclusive to lower caches = false
1923	complex cache indexing = false
1924	number of sets - 1 (s) = 511
1925	--- cache 3 ---
1926	cache type = unified cache (3)
1927	cache level = 0x3 (3)
1928	self-initializing cache level = true
1929	fully associative cache = false
1930	extra threads sharing this cache = 0xf (15)
1931	extra processor cores on this die = 0x7 (7)
1932	system coherency line size = 0x3f (63)
1933	physical line partitions = 0x0 (0)
1934	ways of associativity = 0xb (11)
1935	WBINVD/INVD behavior on lower caches = false
1936	inclusive to lower caches = true
1937	complex cache indexing = true
1938	number of sets - 1 (s) = 8191
1939	--- cache 4 ---
1940	cache type = unified cache (3)
1941	cache level = 0x4 (4)
1942	self-initializing cache level = true
1943	fully associative cache = false
1944	extra threads sharing this cache = 0xf (15)
1945	extra processor cores on this die = 0x7 (7)
1946	system coherency line size = 0x3f (63)
1947	physical line partitions = 0xf (15)
1948	ways of associativity = 0xf (15)
1949	WBINVD/INVD behavior on lower caches = false
1950	inclusive to lower caches = false
1951	complex cache indexing = true
1952	number of sets - 1 (s) = 8191
1953	MONITOR/MWAIT (5):
1954	smallest monitor-line size (bytes) = 0x40 (64)
1955	largest monitor-line size (bytes) = 0x40 (64)
1956	enum of Monitor-MWAIT exts supported = true
1957	supports intrs as break-event for MWAIT = true
1958	number of C0 sub C-states using MWAIT = 0x0 (0)
1959	number of C1 sub C-states using MWAIT = 0x2 (2)
1960	number of C2 sub C-states using MWAIT = 0x1 (1)
1961	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
1962	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
1963	Thermal and Power Management Features (6):
1964	digital thermometer = true
1965	Intel Turbo Boost Technology = true
1966	ARAT always running APIC timer = true
1967	PLN power limit notification = true
1968	ECMD extended clock modulation duty = true
1969	PTM package thermal management = true
1970	digital thermometer thresholds = 0x2 (2)
1971	ACNT/MCNT supported performance measure = true
1972	ACNT2 available = false
1973	performance-energy bias capability = true
1974	extended feature flags (7):
1975	FSGSBASE instructions = true
1976	BMI instruction = true
1977	SMEP support = true
1978	enhanced REP MOVSB/STOSB = true
1979	INVPCID instruction = true
1980	Direct Cache Access Parameters (9):
1981	PLATFORM_DCA_CAP MSR bits = 0
1982	Architecture Performance Monitoring Features (0xa/eax):
1983	version ID = 0x3 (3)
1984	number of counters per logical processor = 0x4 (4)
1985	bit width of counter = 0x30 (48)
1986	length of EBX bit vector = 0x7 (7)
1987	Architecture Performance Monitoring Features (0xa/ebx):
1988	core cycle event not available = false
1989	instruction retired event not available = false
1990	reference cycles event not available = false
1991	last-level cache ref event not available = false
1992	last-level cache miss event not avail = false
1993	branch inst retired event not available = false
1994	branch mispred retired event not avail = false
1995	Architecture Performance Monitoring Features (0xa/edx):
1996	number of fixed counters = 0x3 (3)
1997	bit width of fixed counters = 0x30 (48)
1998	x2APIC features / processor topology (0xb):
1999	--- level 0 (thread) ---
2000	bits to shift APIC ID to get next = 0x1 (1)
2001	logical processors at this level = 0x2 (2)
2002	level number = 0x0 (0)
2003	level type = thread (1)
2004	extended APIC ID = 5
2005	--- level 1 (core) ---
2006	bits to shift APIC ID to get next = 0x4 (4)
2007	logical processors at this level = 0x8 (8)
2008	level number = 0x1 (1)
2009	level type = core (2)
2010	extended APIC ID = 5
2011	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
2012	XSAVE features (0xd/0):
2013	XCR0 lower 32 bits valid bit field mask = 0x00000007
2014	bytes required by fields in XCR0 = 0x00000340 (832)
2015	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
2016	XCR0 upper 32 bits valid bit field mask = 0x00000000
2017	YMM features (0xd/2):
2018	YMM save state byte size = 0x00000100 (256)
2019	YMM save state byte offset = 0x00000240 (576)
2020	LWP features (0xd/0x3e):
2021	LWP save state byte size = 0x00000000 (0)
2022	LWP save state byte offset = 0x00000000 (0)
2023	extended feature flags (0x80000001/edx):
2024	SYSCALL and SYSRET instructions = true
2025	execution disable = true
2026	1-GB large page support = true
2027	RDTSCP = true
2028	64-bit extensions technology available = true
2029	Intel feature flags (0x80000001/ecx):
2030	LAHF/SAHF supported in 64-bit mode = true
2031	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
2032	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
2033	instruction # entries = 0x0 (0)
2034	instruction associativity = 0x0 (0)
2035	data # entries = 0x0 (0)
2036	data associativity = 0x0 (0)
2037	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
2038	instruction # entries = 0x0 (0)
2039	instruction associativity = 0x0 (0)
2040	data # entries = 0x0 (0)
2041	data associativity = 0x0 (0)
2042	L1 data cache information (0x80000005/ecx):
2043	line size (bytes) = 0x0 (0)
2044	lines per tag = 0x0 (0)
2045	associativity = 0x0 (0)
2046	size (Kb) = 0x0 (0)
2047	L1 instruction cache information (0x80000005/edx):
2048	line size (bytes) = 0x0 (0)
2049	lines per tag = 0x0 (0)
2050	associativity = 0x0 (0)
2051	size (Kb) = 0x0 (0)
2052	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
2053	instruction # entries = 0x0 (0)
2054	instruction associativity = L2 off (0)
2055	data # entries = 0x0 (0)
2056	data associativity = L2 off (0)
2057	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
2058	instruction # entries = 0x0 (0)
2059	instruction associativity = L2 off (0)
2060	data # entries = 0x0 (0)
2061	data associativity = L2 off (0)
2062	L2 unified cache information (0x80000006/ecx):
2063	line size (bytes) = 0x40 (64)
2064	lines per tag = 0x0 (0)
2065	associativity = 8-way (6)
2066	size (Kb) = 0x100 (256)
2067	L3 cache information (0x80000006/edx):
2068	line size (bytes) = 0x0 (0)
2069	lines per tag = 0x0 (0)
2070	associativity = L2 off (0)
2071	size (in 512Kb units) = 0x0 (0)
2072	Advanced Power Management Features (0x80000007/edx):
2073	temperature sensing diode = false
2074	frequency ID (FID) control = false
2075	voltage ID (VID) control = false
2076	thermal trip (TTP) = false
2077	thermal monitor (TM) = false
2078	software thermal control (STC) = false
2079	100 MHz multiplier control = false
2080	hardware P-State control = false
2081	TscInvariant = true
2082	Physical Address and Linear Address Size (0x80000008/eax):
2083	maximum physical address bits = 0x27 (39)
2084	maximum linear (virtual) address bits = 0x30 (48)
2085	maximum guest physical address bits = 0x0 (0)
2086	Logical CPU cores (0x80000008/ecx):
2087	number of CPU cores - 1 = 0x0 (0)
2088	ApicIdCoreIdSize = 0x0 (0)
2089	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
2090	(multi-processing method): Intel leaf 0xb
2091	(APIC widths synth): CORE_width=4 SMT_width=1
2092	(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
2093	(synth) = Intel Core (unknown model)
2094	CPU 7:
2095	vendor_id = "GenuineIntel"
2096	version information (1/eax):
2097	processor type = primary processor (0)
2098	family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
2099	model = 0x6 (6)
2100	stepping id = 0x1 (1)
2101	extended family = 0x0 (0)
2102	extended model = 0x4 (4)
2103	(simple synth) = Intel Pentium II / Pentium III / Pentium M / Celeron / Celeron M / Core / Core 2 / Core i / Xeon / Atom (unknown model)
2104	miscellaneous (1/ebx):
2105	process local APIC physical ID = 0x7 (7)
2106	cpu count = 0x10 (16)
2107	CLFLUSH line size = 0x8 (8)
2108	brand index = 0x0 (0)
2109	brand id = 0x00 (0): unknown
2110	feature information (1/edx):
2111	x87 FPU on chip = true
2112	virtual-8086 mode enhancement = true
2113	debugging extensions = true
2114	page size extensions = true
2115	time stamp counter = true
2116	RDMSR and WRMSR support = true
2117	physical address extensions = true
2118	machine check exception = true
2119	CMPXCHG8B inst. = true
2120	APIC on chip = true
2121	SYSENTER and SYSEXIT = true
2122	memory type range registers = true
2123	PTE global bit = true
2124	machine check architecture = true
2125	conditional move/compare instruction = true
2126	page attribute table = true
2127	page size extension = true
2128	processor serial number = false
2129	CLFLUSH instruction = true
2130	debug store = true
2131	thermal monitor and clock ctrl = true
2132	MMX Technology = true
2133	FXSAVE/FXRSTOR = true
2134	SSE extensions = true
2135	SSE2 extensions = true
2136	self snoop = true
2137	hyper-threading / multi-core supported = true
2138	therm. monitor = true
2139	IA64 = false
2140	pending break event = true
2141	feature information (1/ecx):
2142	PNI/SSE3: Prescott New Instructions = true
2143	PCLMULDQ instruction = true
2144	64-bit debug store = true
2145	MONITOR/MWAIT = true
2146	CPL-qualified debug store = true
2147	VMX: virtual machine extensions = true
2148	SMX: safer mode extensions = false
2149	Enhanced Intel SpeedStep Technology = true
2150	thermal monitor 2 = true
2151	SSSE3 extensions = true
2152	context ID: adaptive or shared L1 data = false
2153	FMA instruction = true
2154	CMPXCHG16B instruction = true
2155	xTPR disable = true
2156	perfmon and debug = true
2157	process context identifiers = true
2158	direct cache access = false
2159	SSE4.1 extensions = true
2160	SSE4.2 extensions = true
2161	extended xAPIC support = true
2162	MOVBE instruction = true
2163	POPCNT instruction = true
2164	time stamp counter deadline = true
2165	AES instruction = true
2166	XSAVE/XSTOR states = true
2167	OS-enabled XSAVE/XSTOR = true
2168	AVX: advanced vector extensions = true
2169	F16C half-precision convert instruction = true
2170	RDRAND instruction = true
2171	hypervisor guest status = false
2172	cache and TLB information (2):
2173	0x63: unknown
2174	0x03: data TLB: 4K pages, 4-way, 64 entries
2175	0x76: instruction TLB: 2M/4M pages, fully, 8 entries
2176	0xff: cache data is in CPUID 4
2177	0xb5: unknown
2178	0xf0: 64 byte prefetching
2179	0xc1: unknown
2180	processor serial number: 0004-0661-0000-0000-0000-0000
2181	deterministic cache parameters (4):
2182	--- cache 0 ---
2183	cache type = data cache (1)
2184	cache level = 0x1 (1)
2185	self-initializing cache level = true
2186	fully associative cache = false
2187	extra threads sharing this cache = 0x1 (1)
2188	extra processor cores on this die = 0x7 (7)
2189	system coherency line size = 0x3f (63)
2190	physical line partitions = 0x0 (0)
2191	ways of associativity = 0x7 (7)
2192	WBINVD/INVD behavior on lower caches = false
2193	inclusive to lower caches = false
2194	complex cache indexing = false
2195	number of sets - 1 (s) = 63
2196	--- cache 1 ---
2197	cache type = instruction cache (2)
2198	cache level = 0x1 (1)
2199	self-initializing cache level = true
2200	fully associative cache = false
2201	extra threads sharing this cache = 0x1 (1)
2202	extra processor cores on this die = 0x7 (7)
2203	system coherency line size = 0x3f (63)
2204	physical line partitions = 0x0 (0)
2205	ways of associativity = 0x7 (7)
2206	WBINVD/INVD behavior on lower caches = false
2207	inclusive to lower caches = false
2208	complex cache indexing = false
2209	number of sets - 1 (s) = 63
2210	--- cache 2 ---
2211	cache type = unified cache (3)
2212	cache level = 0x2 (2)
2213	self-initializing cache level = true
2214	fully associative cache = false
2215	extra threads sharing this cache = 0x1 (1)
2216	extra processor cores on this die = 0x7 (7)
2217	system coherency line size = 0x3f (63)
2218	physical line partitions = 0x0 (0)
2219	ways of associativity = 0x7 (7)
2220	WBINVD/INVD behavior on lower caches = false
2221	inclusive to lower caches = false
2222	complex cache indexing = false
2223	number of sets - 1 (s) = 511
2224	--- cache 3 ---
2225	cache type = unified cache (3)
2226	cache level = 0x3 (3)
2227	self-initializing cache level = true
2228	fully associative cache = false
2229	extra threads sharing this cache = 0xf (15)
2230	extra processor cores on this die = 0x7 (7)
2231	system coherency line size = 0x3f (63)
2232	physical line partitions = 0x0 (0)
2233	ways of associativity = 0xb (11)
2234	WBINVD/INVD behavior on lower caches = false
2235	inclusive to lower caches = true
2236	complex cache indexing = true
2237	number of sets - 1 (s) = 8191
2238	--- cache 4 ---
2239	cache type = unified cache (3)
2240	cache level = 0x4 (4)
2241	self-initializing cache level = true
2242	fully associative cache = false
2243	extra threads sharing this cache = 0xf (15)
2244	extra processor cores on this die = 0x7 (7)
2245	system coherency line size = 0x3f (63)
2246	physical line partitions = 0xf (15)
2247	ways of associativity = 0xf (15)
2248	WBINVD/INVD behavior on lower caches = false
2249	inclusive to lower caches = false
2250	complex cache indexing = true
2251	number of sets - 1 (s) = 8191
2252	MONITOR/MWAIT (5):
2253	smallest monitor-line size (bytes) = 0x40 (64)
2254	largest monitor-line size (bytes) = 0x40 (64)
2255	enum of Monitor-MWAIT exts supported = true
2256	supports intrs as break-event for MWAIT = true
2257	number of C0 sub C-states using MWAIT = 0x0 (0)
2258	number of C1 sub C-states using MWAIT = 0x2 (2)
2259	number of C2 sub C-states using MWAIT = 0x1 (1)
2260	number of C3/C6 sub C-states using MWAIT = 0x2 (2)
2261	number of C4/C7 sub C-states using MWAIT = 0x4 (4)
2262	Thermal and Power Management Features (6):
2263	digital thermometer = true
2264	Intel Turbo Boost Technology = true
2265	ARAT always running APIC timer = true
2266	PLN power limit notification = true
2267	ECMD extended clock modulation duty = true
2268	PTM package thermal management = true
2269	digital thermometer thresholds = 0x2 (2)
2270	ACNT/MCNT supported performance measure = true
2271	ACNT2 available = false
2272	performance-energy bias capability = true
2273	extended feature flags (7):
2274	FSGSBASE instructions = true
2275	BMI instruction = true
2276	SMEP support = true
2277	enhanced REP MOVSB/STOSB = true
2278	INVPCID instruction = true
2279	Direct Cache Access Parameters (9):
2280	PLATFORM_DCA_CAP MSR bits = 0
2281	Architecture Performance Monitoring Features (0xa/eax):
2282	version ID = 0x3 (3)
2283	number of counters per logical processor = 0x4 (4)
2284	bit width of counter = 0x30 (48)
2285	length of EBX bit vector = 0x7 (7)
2286	Architecture Performance Monitoring Features (0xa/ebx):
2287	core cycle event not available = false
2288	instruction retired event not available = false
2289	reference cycles event not available = false
2290	last-level cache ref event not available = false
2291	last-level cache miss event not avail = false
2292	branch inst retired event not available = false
2293	branch mispred retired event not avail = false
2294	Architecture Performance Monitoring Features (0xa/edx):
2295	number of fixed counters = 0x3 (3)
2296	bit width of fixed counters = 0x30 (48)
2297	x2APIC features / processor topology (0xb):
2298	--- level 0 (thread) ---
2299	bits to shift APIC ID to get next = 0x1 (1)
2300	logical processors at this level = 0x2 (2)
2301	level number = 0x0 (0)
2302	level type = thread (1)
2303	extended APIC ID = 7
2304	--- level 1 (core) ---
2305	bits to shift APIC ID to get next = 0x4 (4)
2306	logical processors at this level = 0x8 (8)
2307	level number = 0x1 (1)
2308	level type = core (2)
2309	extended APIC ID = 7
2310	0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
2311	XSAVE features (0xd/0):
2312	XCR0 lower 32 bits valid bit field mask = 0x00000007
2313	bytes required by fields in XCR0 = 0x00000340 (832)
2314	bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
2315	XCR0 upper 32 bits valid bit field mask = 0x00000000
2316	YMM features (0xd/2):
2317	YMM save state byte size = 0x00000100 (256)
2318	YMM save state byte offset = 0x00000240 (576)
2319	LWP features (0xd/0x3e):
2320	LWP save state byte size = 0x00000000 (0)
2321	LWP save state byte offset = 0x00000000 (0)
2322	extended feature flags (0x80000001/edx):
2323	SYSCALL and SYSRET instructions = true
2324	execution disable = true
2325	1-GB large page support = true
2326	RDTSCP = true
2327	64-bit extensions technology available = true
2328	Intel feature flags (0x80000001/ecx):
2329	LAHF/SAHF supported in 64-bit mode = true
2330	brand = "Intel(R) Core(TM) i7-4750HQ CPU @ 2.00GHz"
2331	L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
2332	instruction # entries = 0x0 (0)
2333	instruction associativity = 0x0 (0)
2334	data # entries = 0x0 (0)
2335	data associativity = 0x0 (0)
2336	L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
2337	instruction # entries = 0x0 (0)
2338	instruction associativity = 0x0 (0)
2339	data # entries = 0x0 (0)
2340	data associativity = 0x0 (0)
2341	L1 data cache information (0x80000005/ecx):
2342	line size (bytes) = 0x0 (0)
2343	lines per tag = 0x0 (0)
2344	associativity = 0x0 (0)
2345	size (Kb) = 0x0 (0)
2346	L1 instruction cache information (0x80000005/edx):
2347	line size (bytes) = 0x0 (0)
2348	lines per tag = 0x0 (0)
2349	associativity = 0x0 (0)
2350	size (Kb) = 0x0 (0)
2351	L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
2352	instruction # entries = 0x0 (0)
2353	instruction associativity = L2 off (0)
2354	data # entries = 0x0 (0)
2355	data associativity = L2 off (0)
2356	L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
2357	instruction # entries = 0x0 (0)
2358	instruction associativity = L2 off (0)
2359	data # entries = 0x0 (0)
2360	data associativity = L2 off (0)
2361	L2 unified cache information (0x80000006/ecx):
2362	line size (bytes) = 0x40 (64)
2363	lines per tag = 0x0 (0)
2364	associativity = 8-way (6)
2365	size (Kb) = 0x100 (256)
2366	L3 cache information (0x80000006/edx):
2367	line size (bytes) = 0x0 (0)
2368	lines per tag = 0x0 (0)
2369	associativity = L2 off (0)
2370	size (in 512Kb units) = 0x0 (0)
2371	Advanced Power Management Features (0x80000007/edx):
2372	temperature sensing diode = false
2373	frequency ID (FID) control = false
2374	voltage ID (VID) control = false
2375	thermal trip (TTP) = false
2376	thermal monitor (TM) = false
2377	software thermal control (STC) = false
2378	100 MHz multiplier control = false
2379	hardware P-State control = false
2380	TscInvariant = true
2381	Physical Address and Linear Address Size (0x80000008/eax):
2382	maximum physical address bits = 0x27 (39)
2383	maximum linear (virtual) address bits = 0x30 (48)
2384	maximum guest physical address bits = 0x0 (0)
2385	Logical CPU cores (0x80000008/ecx):
2386	number of CPU cores - 1 = 0x0 (0)
2387	ApicIdCoreIdSize = 0x0 (0)
2388	(multi-processing synth): multi-core (c=4), hyper-threaded (t=2)
2389	(multi-processing method): Intel leaf 0xb
2390	(APIC widths synth): CORE_width=4 SMT_width=1
2391	(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
2392	(synth) = Intel Core (unknown model)

Download in other formats:

Original Format