| 1 | CPU 0:
|
|---|
| 2 | vendor_id = "GenuineIntel"
|
|---|
| 3 | version information (1/eax):
|
|---|
| 4 | processor type = primary processor (0)
|
|---|
| 5 | family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
|
|---|
| 6 | model = 0x7 (7)
|
|---|
| 7 | stepping id = 0xa (10)
|
|---|
| 8 | extended family = 0x0 (0)
|
|---|
| 9 | extended model = 0x1 (1)
|
|---|
| 10 | (simple synth) = Intel Core 2 Duo (Wolfdale E0/R0) / Core 2 Quad-Core Q9000 (Yorkfield E0/R0) / Mobile Core 2 (Penryn E0/R0) / Pentium Dual-Core Processor E5000/E600 (Wolfdale R0) / Celeron E3000 (Wolfdale R0) / Xeon Processor 3100 (Wolfdale E0) / Xeon Processor 3300 (Yorkfield E0/R0) / Xeon Processor 5200 (Wolfdale E0) / Xeon Processor 5400 (Harpertown E0), 45nm
|
|---|
| 11 | miscellaneous (1/ebx):
|
|---|
| 12 | process local APIC physical ID = 0x0 (0)
|
|---|
| 13 | cpu count = 0x2 (2)
|
|---|
| 14 | CLFLUSH line size = 0x8 (8)
|
|---|
| 15 | brand index = 0x0 (0)
|
|---|
| 16 | brand id = 0x00 (0): unknown
|
|---|
| 17 | feature information (1/edx):
|
|---|
| 18 | x87 FPU on chip = true
|
|---|
| 19 | VME: virtual-8086 mode enhancement = true
|
|---|
| 20 | DE: debugging extensions = true
|
|---|
| 21 | PSE: page size extensions = true
|
|---|
| 22 | TSC: time stamp counter = true
|
|---|
| 23 | RDMSR and WRMSR support = true
|
|---|
| 24 | PAE: physical address extensions = true
|
|---|
| 25 | MCE: machine check exception = true
|
|---|
| 26 | CMPXCHG8B inst. = true
|
|---|
| 27 | APIC on chip = true
|
|---|
| 28 | SYSENTER and SYSEXIT = true
|
|---|
| 29 | MTRR: memory type range registers = true
|
|---|
| 30 | PTE global bit = true
|
|---|
| 31 | MCA: machine check architecture = true
|
|---|
| 32 | CMOV: conditional move/compare instr = true
|
|---|
| 33 | PAT: page attribute table = true
|
|---|
| 34 | PSE-36: page size extension = true
|
|---|
| 35 | PSN: processor serial number = false
|
|---|
| 36 | CLFLUSH instruction = true
|
|---|
| 37 | DS: debug store = true
|
|---|
| 38 | ACPI: thermal monitor and clock ctrl = true
|
|---|
| 39 | MMX Technology = true
|
|---|
| 40 | FXSAVE/FXRSTOR = true
|
|---|
| 41 | SSE extensions = true
|
|---|
| 42 | SSE2 extensions = true
|
|---|
| 43 | SS: self snoop = true
|
|---|
| 44 | hyper-threading / multi-core supported = true
|
|---|
| 45 | TM: therm. monitor = true
|
|---|
| 46 | IA64 = false
|
|---|
| 47 | PBE: pending break event = true
|
|---|
| 48 | feature information (1/ecx):
|
|---|
| 49 | PNI/SSE3: Prescott New Instructions = true
|
|---|
| 50 | PCLMULDQ instruction = false
|
|---|
| 51 | DTES64: 64-bit debug store = true
|
|---|
| 52 | MONITOR/MWAIT = true
|
|---|
| 53 | CPL-qualified debug store = true
|
|---|
| 54 | VMX: virtual machine extensions = true
|
|---|
| 55 | SMX: safer mode extensions = false
|
|---|
| 56 | Enhanced Intel SpeedStep Technology = true
|
|---|
| 57 | TM2: thermal monitor 2 = true
|
|---|
| 58 | SSSE3 extensions = true
|
|---|
| 59 | context ID: adaptive or shared L1 data = false
|
|---|
| 60 | SDBG: IA32_DEBUG_INTERFACE = false
|
|---|
| 61 | FMA instruction = false
|
|---|
| 62 | CMPXCHG16B instruction = true
|
|---|
| 63 | xTPR disable = true
|
|---|
| 64 | PDCM: perfmon and debug = true
|
|---|
| 65 | PCID: process context identifiers = false
|
|---|
| 66 | DCA: direct cache access = false
|
|---|
| 67 | SSE4.1 extensions = false
|
|---|
| 68 | SSE4.2 extensions = false
|
|---|
| 69 | x2APIC: extended xAPIC support = false
|
|---|
| 70 | MOVBE instruction = false
|
|---|
| 71 | POPCNT instruction = false
|
|---|
| 72 | time stamp counter deadline = false
|
|---|
| 73 | AES instruction = false
|
|---|
| 74 | XSAVE/XSTOR states = true
|
|---|
| 75 | OS-enabled XSAVE/XSTOR = true
|
|---|
| 76 | AVX: advanced vector extensions = false
|
|---|
| 77 | F16C half-precision convert instruction = false
|
|---|
| 78 | RDRAND instruction = false
|
|---|
| 79 | hypervisor guest status = false
|
|---|
| 80 | cache and TLB information (2):
|
|---|
| 81 | 0xb1: instruction TLB: 2M/4M, 4-way, 4/8 entries
|
|---|
| 82 | 0xb0: instruction TLB: 4K, 4-way, 128 entries
|
|---|
| 83 | 0x05: data TLB: 4M pages, 4-way, 32 entries
|
|---|
| 84 | 0xf0: 64 byte prefetching
|
|---|
| 85 | 0x57: L1 data TLB: 4K pages, 4-way, 16 entries
|
|---|
| 86 | 0x56: L1 data TLB: 4M pages, 4-way, 16 entries
|
|---|
| 87 | 0x78: L2 cache: 1M, 4-way, 64 byte lines
|
|---|
| 88 | 0x30: L1 cache: 32K, 8-way, 64 byte lines
|
|---|
| 89 | 0xb4: data TLB: 4K pages, 4-way, 256 entries
|
|---|
| 90 | 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
|
|---|
| 91 | processor serial number: 0001-067A-0000-0000-0000-0000
|
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| 92 | deterministic cache parameters (4):
|
|---|
| 93 | --- cache 0 ---
|
|---|
| 94 | cache type = data cache (1)
|
|---|
| 95 | cache level = 0x1 (1)
|
|---|
| 96 | self-initializing cache level = true
|
|---|
| 97 | fully associative cache = false
|
|---|
| 98 | extra threads sharing this cache = 0x0 (0)
|
|---|
| 99 | extra processor cores on this die = 0x1 (1)
|
|---|
| 100 | system coherency line size = 0x3f (63)
|
|---|
| 101 | physical line partitions = 0x0 (0)
|
|---|
| 102 | ways of associativity = 0x7 (7)
|
|---|
| 103 | number of sets - 1 = 0x3f (63)
|
|---|
| 104 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 105 | inclusive to lower caches = false
|
|---|
| 106 | complex cache indexing = false
|
|---|
| 107 | number of sets - 1 (s) = 63
|
|---|
| 108 | --- cache 1 ---
|
|---|
| 109 | cache type = instruction cache (2)
|
|---|
| 110 | cache level = 0x1 (1)
|
|---|
| 111 | self-initializing cache level = true
|
|---|
| 112 | fully associative cache = false
|
|---|
| 113 | extra threads sharing this cache = 0x0 (0)
|
|---|
| 114 | extra processor cores on this die = 0x1 (1)
|
|---|
| 115 | system coherency line size = 0x3f (63)
|
|---|
| 116 | physical line partitions = 0x0 (0)
|
|---|
| 117 | ways of associativity = 0x7 (7)
|
|---|
| 118 | number of sets - 1 = 0x3f (63)
|
|---|
| 119 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 120 | inclusive to lower caches = false
|
|---|
| 121 | complex cache indexing = false
|
|---|
| 122 | number of sets - 1 (s) = 63
|
|---|
| 123 | --- cache 2 ---
|
|---|
| 124 | cache type = unified cache (3)
|
|---|
| 125 | cache level = 0x2 (2)
|
|---|
| 126 | self-initializing cache level = true
|
|---|
| 127 | fully associative cache = false
|
|---|
| 128 | extra threads sharing this cache = 0x1 (1)
|
|---|
| 129 | extra processor cores on this die = 0x1 (1)
|
|---|
| 130 | system coherency line size = 0x3f (63)
|
|---|
| 131 | physical line partitions = 0x0 (0)
|
|---|
| 132 | ways of associativity = 0x3 (3)
|
|---|
| 133 | number of sets - 1 = 0xfff (4095)
|
|---|
| 134 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 135 | inclusive to lower caches = false
|
|---|
| 136 | complex cache indexing = false
|
|---|
| 137 | number of sets - 1 (s) = 4095
|
|---|
| 138 | MONITOR/MWAIT (5):
|
|---|
| 139 | smallest monitor-line size (bytes) = 0x40 (64)
|
|---|
| 140 | largest monitor-line size (bytes) = 0x40 (64)
|
|---|
| 141 | enum of Monitor-MWAIT exts supported = true
|
|---|
| 142 | supports intrs as break-event for MWAIT = true
|
|---|
| 143 | number of C0 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 144 | number of C1 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 145 | number of C2 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 146 | number of C3 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 147 | number of C4 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 148 | number of C5 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 149 | number of C6 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 150 | number of C7 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 151 | Thermal and Power Management Features (6):
|
|---|
| 152 | digital thermometer = true
|
|---|
| 153 | Intel Turbo Boost Technology = false
|
|---|
| 154 | ARAT always running APIC timer = false
|
|---|
| 155 | PLN power limit notification = false
|
|---|
| 156 | ECMD extended clock modulation duty = false
|
|---|
| 157 | PTM package thermal management = false
|
|---|
| 158 | HWP base registers = false
|
|---|
| 159 | HWP notification = false
|
|---|
| 160 | HWP activity window = false
|
|---|
| 161 | HWP energy performance preference = false
|
|---|
| 162 | HWP package level request = false
|
|---|
| 163 | HDC base registers = false
|
|---|
| 164 | Intel Turbo Boost Max Technology 3.0 = false
|
|---|
| 165 | HWP capabilities = false
|
|---|
| 166 | HWP PECI override = false
|
|---|
| 167 | flexible HWP = false
|
|---|
| 168 | IA32_HWP_REQUEST MSR fast access mode = false
|
|---|
| 169 | ignoring idle logical processor HWP req = false
|
|---|
| 170 | digital thermometer thresholds = 0x2 (2)
|
|---|
| 171 | hardware coordination feedback = true
|
|---|
| 172 | ACNT2 available = true
|
|---|
| 173 | performance-energy bias capability = false
|
|---|
| 174 | extended feature flags (7):
|
|---|
| 175 | FSGSBASE instructions = false
|
|---|
| 176 | IA32_TSC_ADJUST MSR supported = false
|
|---|
| 177 | SGX: Software Guard Extensions supported = false
|
|---|
| 178 | BMI1 instructions = false
|
|---|
| 179 | HLE hardware lock elision = false
|
|---|
| 180 | AVX2: advanced vector extensions 2 = false
|
|---|
| 181 | FDP_EXCPTN_ONLY = false
|
|---|
| 182 | SMEP supervisor mode exec protection = false
|
|---|
| 183 | BMI2 instructions = false
|
|---|
| 184 | enhanced REP MOVSB/STOSB = false
|
|---|
| 185 | INVPCID instruction = false
|
|---|
| 186 | RTM: restricted transactional memory = false
|
|---|
| 187 | RDT-M: Intel RDT monitoring = false
|
|---|
| 188 | deprecated FPU CS/DS = false
|
|---|
| 189 | MPX: intel memory protection extensions = false
|
|---|
| 190 | RDT-A: Intel RDT allocation = false
|
|---|
| 191 | AVX512F: AVX-512 foundation instructions = false
|
|---|
| 192 | AVX512DQ: double & quadword instructions = false
|
|---|
| 193 | RDSEED instruction = false
|
|---|
| 194 | ADX instructions = false
|
|---|
| 195 | SMAP: supervisor mode access prevention = false
|
|---|
| 196 | AVX512IFMA: fused multiply add = false
|
|---|
| 197 | CLFLUSHOPT instruction = false
|
|---|
| 198 | CLWB instruction = false
|
|---|
| 199 | Intel processor trace = false
|
|---|
| 200 | AVX512PF: prefetch instructions = false
|
|---|
| 201 | AVX512ER: exponent & reciprocal instrs = false
|
|---|
| 202 | AVX512CD: conflict detection instrs = false
|
|---|
| 203 | SHA instructions = false
|
|---|
| 204 | AVX512BW: byte & word instructions = false
|
|---|
| 205 | AVX512VL: vector length = false
|
|---|
| 206 | PREFETCHWT1 = false
|
|---|
| 207 | AVX512VBMI: vector byte manipulation = false
|
|---|
| 208 | UMIP: user-mode instruction prevention = false
|
|---|
| 209 | PKU protection keys for user-mode = false
|
|---|
| 210 | OSPKE CR4.PKE and RDPKRU/WRPKRU = false
|
|---|
| 211 | WAITPKG instructions = false
|
|---|
| 212 | AVX512_VBMI2 = false
|
|---|
| 213 | GFNI: Galois Field New Instructions = false
|
|---|
| 214 | VAES instructions = false
|
|---|
| 215 | VPCLMULQDQ instruction = false
|
|---|
| 216 | AVX512_VNNI = false
|
|---|
| 217 | AVX512_BITALG: bit count/shiffle = false
|
|---|
| 218 | AVX512: VPOPCNTDQ instruction = false
|
|---|
| 219 | BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
|
|---|
| 220 | RDPID: read processor D supported = false
|
|---|
| 221 | CLDEMOTE supports cache line demote = false
|
|---|
| 222 | MOVDIRI instruction = false
|
|---|
| 223 | MOVDIR64B intruction = false
|
|---|
| 224 | SGX_LC: SGX launch config supported = false
|
|---|
| 225 | AVX512_4VNNIW: neural network instrs = false
|
|---|
| 226 | AVX512_4FMAPS: multiply acc single prec = false
|
|---|
| 227 | fast short REP MOV = false
|
|---|
| 228 | PCONFIG = false
|
|---|
| 229 | Direct Cache Access Parameters (9):
|
|---|
| 230 | PLATFORM_DCA_CAP MSR bits = 0
|
|---|
| 231 | Architecture Performance Monitoring Features (0xa/eax):
|
|---|
| 232 | version ID = 0x2 (2)
|
|---|
| 233 | number of counters per logical processor = 0x2 (2)
|
|---|
| 234 | bit width of counter = 0x28 (40)
|
|---|
| 235 | length of EBX bit vector = 0x7 (7)
|
|---|
| 236 | Architecture Performance Monitoring Features (0xa/ebx):
|
|---|
| 237 | core cycle event not available = false
|
|---|
| 238 | instruction retired event not available = false
|
|---|
| 239 | reference cycles event not available = false
|
|---|
| 240 | last-level cache ref event not available = false
|
|---|
| 241 | last-level cache miss event not avail = false
|
|---|
| 242 | branch inst retired event not available = false
|
|---|
| 243 | branch mispred retired event not avail = false
|
|---|
| 244 | Architecture Performance Monitoring Features (0xa/edx):
|
|---|
| 245 | number of fixed counters = 0x3 (3)
|
|---|
| 246 | bit width of fixed counters = 0x28 (40)
|
|---|
| 247 | anythread deprecation = false
|
|---|
| 248 | XSAVE features (0xd/0):
|
|---|
| 249 | XCR0 lower 32 bits valid bit field mask = 0x00000003
|
|---|
| 250 | XCR0 upper 32 bits valid bit field mask = 0x00000000
|
|---|
| 251 | XCR0 supported: x87 state = true
|
|---|
| 252 | XCR0 supported: SSE state = true
|
|---|
| 253 | XCR0 supported: AVX state = false
|
|---|
| 254 | XCR0 supported: MPX BNDREGS = false
|
|---|
| 255 | XCR0 supported: MPX BNDCSR = false
|
|---|
| 256 | XCR0 supported: AVX-512 opmask = false
|
|---|
| 257 | XCR0 supported: AVX-512 ZMM_Hi256 = false
|
|---|
| 258 | XCR0 supported: AVX-512 Hi16_ZMM = false
|
|---|
| 259 | IA32_XSS supported: PT state = false
|
|---|
| 260 | XCR0 supported: PKRU state = false
|
|---|
| 261 | IA32_XSS supported: HDC state = false
|
|---|
| 262 | bytes required by fields in XCR0 = 0x00000240 (576)
|
|---|
| 263 | bytes required by XSAVE/XRSTOR area = 0x00000240 (576)
|
|---|
| 264 | XSAVE features (0xd/1):
|
|---|
| 265 | XSAVEOPT instruction = false
|
|---|
| 266 | XSAVEC instruction = false
|
|---|
| 267 | XGETBV instruction = false
|
|---|
| 268 | XSAVES/XRSTORS instructions = false
|
|---|
| 269 | SAVE area size in bytes = 0x00000000 (0)
|
|---|
| 270 | IA32_XSS lower 32 bits valid bit field mask = 0x00000000
|
|---|
| 271 | IA32_XSS upper 32 bits valid bit field mask = 0x00000000
|
|---|
| 272 | extended feature flags (0x80000001/edx):
|
|---|
| 273 | SYSCALL and SYSRET instructions = false
|
|---|
| 274 | execution disable = true
|
|---|
| 275 | 1-GB large page support = false
|
|---|
| 276 | RDTSCP = false
|
|---|
| 277 | 64-bit extensions technology available = true
|
|---|
| 278 | Intel feature flags (0x80000001/ecx):
|
|---|
| 279 | LAHF/SAHF supported in 64-bit mode = true
|
|---|
| 280 | LZCNT advanced bit manipulation = false
|
|---|
| 281 | 3DNow! PREFETCH/PREFETCHW instructions = false
|
|---|
| 282 | brand = "Intel(R) Celeron(R) CPU E3300 @ 2.50GHz"
|
|---|
| 283 | L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
|
|---|
| 284 | instruction # entries = 0x0 (0)
|
|---|
| 285 | instruction associativity = 0x0 (0)
|
|---|
| 286 | data # entries = 0x0 (0)
|
|---|
| 287 | data associativity = 0x0 (0)
|
|---|
| 288 | L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
|
|---|
| 289 | instruction # entries = 0x0 (0)
|
|---|
| 290 | instruction associativity = 0x0 (0)
|
|---|
| 291 | data # entries = 0x0 (0)
|
|---|
| 292 | data associativity = 0x0 (0)
|
|---|
| 293 | L1 data cache information (0x80000005/ecx):
|
|---|
| 294 | line size (bytes) = 0x0 (0)
|
|---|
| 295 | lines per tag = 0x0 (0)
|
|---|
| 296 | associativity = 0x0 (0)
|
|---|
| 297 | size (KB) = 0x0 (0)
|
|---|
| 298 | L1 instruction cache information (0x80000005/edx):
|
|---|
| 299 | line size (bytes) = 0x0 (0)
|
|---|
| 300 | lines per tag = 0x0 (0)
|
|---|
| 301 | associativity = 0x0 (0)
|
|---|
| 302 | size (KB) = 0x0 (0)
|
|---|
| 303 | L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
|
|---|
| 304 | instruction # entries = 0x0 (0)
|
|---|
| 305 | instruction associativity = L2 off (0)
|
|---|
| 306 | data # entries = 0x0 (0)
|
|---|
| 307 | data associativity = L2 off (0)
|
|---|
| 308 | L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
|
|---|
| 309 | instruction # entries = 0x0 (0)
|
|---|
| 310 | instruction associativity = L2 off (0)
|
|---|
| 311 | data # entries = 0x0 (0)
|
|---|
| 312 | data associativity = L2 off (0)
|
|---|
| 313 | L2 unified cache information (0x80000006/ecx):
|
|---|
| 314 | line size (bytes) = 0x40 (64)
|
|---|
| 315 | lines per tag = 0x0 (0)
|
|---|
| 316 | associativity = 4-way (4)
|
|---|
| 317 | size (KB) = 0x400 (1024)
|
|---|
| 318 | L3 cache information (0x80000006/edx):
|
|---|
| 319 | line size (bytes) = 0x0 (0)
|
|---|
| 320 | lines per tag = 0x0 (0)
|
|---|
| 321 | associativity = L2 off (0)
|
|---|
| 322 | size (in 512KB units) = 0x0 (0)
|
|---|
| 323 | Advanced Power Management Features (0x80000007/edx):
|
|---|
| 324 | temperature sensing diode = false
|
|---|
| 325 | frequency ID (FID) control = false
|
|---|
| 326 | voltage ID (VID) control = false
|
|---|
| 327 | thermal trip (TTP) = false
|
|---|
| 328 | thermal monitor (TM) = false
|
|---|
| 329 | software thermal control (STC) = false
|
|---|
| 330 | 100 MHz multiplier control = false
|
|---|
| 331 | hardware P-State control = false
|
|---|
| 332 | TscInvariant = false
|
|---|
| 333 | Physical Address and Linear Address Size (0x80000008/eax):
|
|---|
| 334 | maximum physical address bits = 0x24 (36)
|
|---|
| 335 | maximum linear (virtual) address bits = 0x30 (48)
|
|---|
| 336 | maximum guest physical address bits = 0x0 (0)
|
|---|
| 337 | Logical CPU cores (0x80000008/ecx):
|
|---|
| 338 | number of CPU cores - 1 = 0x0 (0)
|
|---|
| 339 | ApicIdCoreIdSize = 0x0 (0)
|
|---|
| 340 | (multi-processing synth): multi-core (c=2)
|
|---|
| 341 | (multi-processing method): Intel leaf 1/4
|
|---|
| 342 | (APIC widths synth): CORE_width=1 SMT_width=0
|
|---|
| 343 | (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
|
|---|
| 344 | (synth) = Intel Celeron E3000 (Wolfdale R0), 45nm
|
|---|
| 345 | CPU 1:
|
|---|
| 346 | vendor_id = "GenuineIntel"
|
|---|
| 347 | version information (1/eax):
|
|---|
| 348 | processor type = primary processor (0)
|
|---|
| 349 | family = Intel Pentium Pro/II/III/Celeron/Core/Core 2/Atom, AMD Athlon/Duron, Cyrix M2, VIA C3 (6)
|
|---|
| 350 | model = 0x7 (7)
|
|---|
| 351 | stepping id = 0xa (10)
|
|---|
| 352 | extended family = 0x0 (0)
|
|---|
| 353 | extended model = 0x1 (1)
|
|---|
| 354 | (simple synth) = Intel Core 2 Duo (Wolfdale E0/R0) / Core 2 Quad-Core Q9000 (Yorkfield E0/R0) / Mobile Core 2 (Penryn E0/R0) / Pentium Dual-Core Processor E5000/E600 (Wolfdale R0) / Celeron E3000 (Wolfdale R0) / Xeon Processor 3100 (Wolfdale E0) / Xeon Processor 3300 (Yorkfield E0/R0) / Xeon Processor 5200 (Wolfdale E0) / Xeon Processor 5400 (Harpertown E0), 45nm
|
|---|
| 355 | miscellaneous (1/ebx):
|
|---|
| 356 | process local APIC physical ID = 0x1 (1)
|
|---|
| 357 | cpu count = 0x2 (2)
|
|---|
| 358 | CLFLUSH line size = 0x8 (8)
|
|---|
| 359 | brand index = 0x0 (0)
|
|---|
| 360 | brand id = 0x00 (0): unknown
|
|---|
| 361 | feature information (1/edx):
|
|---|
| 362 | x87 FPU on chip = true
|
|---|
| 363 | VME: virtual-8086 mode enhancement = true
|
|---|
| 364 | DE: debugging extensions = true
|
|---|
| 365 | PSE: page size extensions = true
|
|---|
| 366 | TSC: time stamp counter = true
|
|---|
| 367 | RDMSR and WRMSR support = true
|
|---|
| 368 | PAE: physical address extensions = true
|
|---|
| 369 | MCE: machine check exception = true
|
|---|
| 370 | CMPXCHG8B inst. = true
|
|---|
| 371 | APIC on chip = true
|
|---|
| 372 | SYSENTER and SYSEXIT = true
|
|---|
| 373 | MTRR: memory type range registers = true
|
|---|
| 374 | PTE global bit = true
|
|---|
| 375 | MCA: machine check architecture = true
|
|---|
| 376 | CMOV: conditional move/compare instr = true
|
|---|
| 377 | PAT: page attribute table = true
|
|---|
| 378 | PSE-36: page size extension = true
|
|---|
| 379 | PSN: processor serial number = false
|
|---|
| 380 | CLFLUSH instruction = true
|
|---|
| 381 | DS: debug store = true
|
|---|
| 382 | ACPI: thermal monitor and clock ctrl = true
|
|---|
| 383 | MMX Technology = true
|
|---|
| 384 | FXSAVE/FXRSTOR = true
|
|---|
| 385 | SSE extensions = true
|
|---|
| 386 | SSE2 extensions = true
|
|---|
| 387 | SS: self snoop = true
|
|---|
| 388 | hyper-threading / multi-core supported = true
|
|---|
| 389 | TM: therm. monitor = true
|
|---|
| 390 | IA64 = false
|
|---|
| 391 | PBE: pending break event = true
|
|---|
| 392 | feature information (1/ecx):
|
|---|
| 393 | PNI/SSE3: Prescott New Instructions = true
|
|---|
| 394 | PCLMULDQ instruction = false
|
|---|
| 395 | DTES64: 64-bit debug store = true
|
|---|
| 396 | MONITOR/MWAIT = true
|
|---|
| 397 | CPL-qualified debug store = true
|
|---|
| 398 | VMX: virtual machine extensions = true
|
|---|
| 399 | SMX: safer mode extensions = false
|
|---|
| 400 | Enhanced Intel SpeedStep Technology = true
|
|---|
| 401 | TM2: thermal monitor 2 = true
|
|---|
| 402 | SSSE3 extensions = true
|
|---|
| 403 | context ID: adaptive or shared L1 data = false
|
|---|
| 404 | SDBG: IA32_DEBUG_INTERFACE = false
|
|---|
| 405 | FMA instruction = false
|
|---|
| 406 | CMPXCHG16B instruction = true
|
|---|
| 407 | xTPR disable = true
|
|---|
| 408 | PDCM: perfmon and debug = true
|
|---|
| 409 | PCID: process context identifiers = false
|
|---|
| 410 | DCA: direct cache access = false
|
|---|
| 411 | SSE4.1 extensions = false
|
|---|
| 412 | SSE4.2 extensions = false
|
|---|
| 413 | x2APIC: extended xAPIC support = false
|
|---|
| 414 | MOVBE instruction = false
|
|---|
| 415 | POPCNT instruction = false
|
|---|
| 416 | time stamp counter deadline = false
|
|---|
| 417 | AES instruction = false
|
|---|
| 418 | XSAVE/XSTOR states = true
|
|---|
| 419 | OS-enabled XSAVE/XSTOR = true
|
|---|
| 420 | AVX: advanced vector extensions = false
|
|---|
| 421 | F16C half-precision convert instruction = false
|
|---|
| 422 | RDRAND instruction = false
|
|---|
| 423 | hypervisor guest status = false
|
|---|
| 424 | cache and TLB information (2):
|
|---|
| 425 | 0xb1: instruction TLB: 2M/4M, 4-way, 4/8 entries
|
|---|
| 426 | 0xb0: instruction TLB: 4K, 4-way, 128 entries
|
|---|
| 427 | 0x05: data TLB: 4M pages, 4-way, 32 entries
|
|---|
| 428 | 0xf0: 64 byte prefetching
|
|---|
| 429 | 0x57: L1 data TLB: 4K pages, 4-way, 16 entries
|
|---|
| 430 | 0x56: L1 data TLB: 4M pages, 4-way, 16 entries
|
|---|
| 431 | 0x78: L2 cache: 1M, 4-way, 64 byte lines
|
|---|
| 432 | 0x30: L1 cache: 32K, 8-way, 64 byte lines
|
|---|
| 433 | 0xb4: data TLB: 4K pages, 4-way, 256 entries
|
|---|
| 434 | 0x2c: L1 data cache: 32K, 8-way, 64 byte lines
|
|---|
| 435 | processor serial number: 0001-067A-0000-0000-0000-0000
|
|---|
| 436 | deterministic cache parameters (4):
|
|---|
| 437 | --- cache 0 ---
|
|---|
| 438 | cache type = data cache (1)
|
|---|
| 439 | cache level = 0x1 (1)
|
|---|
| 440 | self-initializing cache level = true
|
|---|
| 441 | fully associative cache = false
|
|---|
| 442 | extra threads sharing this cache = 0x0 (0)
|
|---|
| 443 | extra processor cores on this die = 0x1 (1)
|
|---|
| 444 | system coherency line size = 0x3f (63)
|
|---|
| 445 | physical line partitions = 0x0 (0)
|
|---|
| 446 | ways of associativity = 0x7 (7)
|
|---|
| 447 | number of sets - 1 = 0x3f (63)
|
|---|
| 448 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 449 | inclusive to lower caches = false
|
|---|
| 450 | complex cache indexing = false
|
|---|
| 451 | number of sets - 1 (s) = 63
|
|---|
| 452 | --- cache 1 ---
|
|---|
| 453 | cache type = instruction cache (2)
|
|---|
| 454 | cache level = 0x1 (1)
|
|---|
| 455 | self-initializing cache level = true
|
|---|
| 456 | fully associative cache = false
|
|---|
| 457 | extra threads sharing this cache = 0x0 (0)
|
|---|
| 458 | extra processor cores on this die = 0x1 (1)
|
|---|
| 459 | system coherency line size = 0x3f (63)
|
|---|
| 460 | physical line partitions = 0x0 (0)
|
|---|
| 461 | ways of associativity = 0x7 (7)
|
|---|
| 462 | number of sets - 1 = 0x3f (63)
|
|---|
| 463 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 464 | inclusive to lower caches = false
|
|---|
| 465 | complex cache indexing = false
|
|---|
| 466 | number of sets - 1 (s) = 63
|
|---|
| 467 | --- cache 2 ---
|
|---|
| 468 | cache type = unified cache (3)
|
|---|
| 469 | cache level = 0x2 (2)
|
|---|
| 470 | self-initializing cache level = true
|
|---|
| 471 | fully associative cache = false
|
|---|
| 472 | extra threads sharing this cache = 0x1 (1)
|
|---|
| 473 | extra processor cores on this die = 0x1 (1)
|
|---|
| 474 | system coherency line size = 0x3f (63)
|
|---|
| 475 | physical line partitions = 0x0 (0)
|
|---|
| 476 | ways of associativity = 0x3 (3)
|
|---|
| 477 | number of sets - 1 = 0xfff (4095)
|
|---|
| 478 | WBINVD/INVD behavior on lower caches = true
|
|---|
| 479 | inclusive to lower caches = false
|
|---|
| 480 | complex cache indexing = false
|
|---|
| 481 | number of sets - 1 (s) = 4095
|
|---|
| 482 | MONITOR/MWAIT (5):
|
|---|
| 483 | smallest monitor-line size (bytes) = 0x40 (64)
|
|---|
| 484 | largest monitor-line size (bytes) = 0x40 (64)
|
|---|
| 485 | enum of Monitor-MWAIT exts supported = true
|
|---|
| 486 | supports intrs as break-event for MWAIT = true
|
|---|
| 487 | number of C0 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 488 | number of C1 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 489 | number of C2 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 490 | number of C3 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 491 | number of C4 sub C-states using MWAIT = 0x2 (2)
|
|---|
| 492 | number of C5 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 493 | number of C6 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 494 | number of C7 sub C-states using MWAIT = 0x0 (0)
|
|---|
| 495 | Thermal and Power Management Features (6):
|
|---|
| 496 | digital thermometer = true
|
|---|
| 497 | Intel Turbo Boost Technology = false
|
|---|
| 498 | ARAT always running APIC timer = false
|
|---|
| 499 | PLN power limit notification = false
|
|---|
| 500 | ECMD extended clock modulation duty = false
|
|---|
| 501 | PTM package thermal management = false
|
|---|
| 502 | HWP base registers = false
|
|---|
| 503 | HWP notification = false
|
|---|
| 504 | HWP activity window = false
|
|---|
| 505 | HWP energy performance preference = false
|
|---|
| 506 | HWP package level request = false
|
|---|
| 507 | HDC base registers = false
|
|---|
| 508 | Intel Turbo Boost Max Technology 3.0 = false
|
|---|
| 509 | HWP capabilities = false
|
|---|
| 510 | HWP PECI override = false
|
|---|
| 511 | flexible HWP = false
|
|---|
| 512 | IA32_HWP_REQUEST MSR fast access mode = false
|
|---|
| 513 | ignoring idle logical processor HWP req = false
|
|---|
| 514 | digital thermometer thresholds = 0x2 (2)
|
|---|
| 515 | hardware coordination feedback = true
|
|---|
| 516 | ACNT2 available = true
|
|---|
| 517 | performance-energy bias capability = false
|
|---|
| 518 | extended feature flags (7):
|
|---|
| 519 | FSGSBASE instructions = false
|
|---|
| 520 | IA32_TSC_ADJUST MSR supported = false
|
|---|
| 521 | SGX: Software Guard Extensions supported = false
|
|---|
| 522 | BMI1 instructions = false
|
|---|
| 523 | HLE hardware lock elision = false
|
|---|
| 524 | AVX2: advanced vector extensions 2 = false
|
|---|
| 525 | FDP_EXCPTN_ONLY = false
|
|---|
| 526 | SMEP supervisor mode exec protection = false
|
|---|
| 527 | BMI2 instructions = false
|
|---|
| 528 | enhanced REP MOVSB/STOSB = false
|
|---|
| 529 | INVPCID instruction = false
|
|---|
| 530 | RTM: restricted transactional memory = false
|
|---|
| 531 | RDT-M: Intel RDT monitoring = false
|
|---|
| 532 | deprecated FPU CS/DS = false
|
|---|
| 533 | MPX: intel memory protection extensions = false
|
|---|
| 534 | RDT-A: Intel RDT allocation = false
|
|---|
| 535 | AVX512F: AVX-512 foundation instructions = false
|
|---|
| 536 | AVX512DQ: double & quadword instructions = false
|
|---|
| 537 | RDSEED instruction = false
|
|---|
| 538 | ADX instructions = false
|
|---|
| 539 | SMAP: supervisor mode access prevention = false
|
|---|
| 540 | AVX512IFMA: fused multiply add = false
|
|---|
| 541 | CLFLUSHOPT instruction = false
|
|---|
| 542 | CLWB instruction = false
|
|---|
| 543 | Intel processor trace = false
|
|---|
| 544 | AVX512PF: prefetch instructions = false
|
|---|
| 545 | AVX512ER: exponent & reciprocal instrs = false
|
|---|
| 546 | AVX512CD: conflict detection instrs = false
|
|---|
| 547 | SHA instructions = false
|
|---|
| 548 | AVX512BW: byte & word instructions = false
|
|---|
| 549 | AVX512VL: vector length = false
|
|---|
| 550 | PREFETCHWT1 = false
|
|---|
| 551 | AVX512VBMI: vector byte manipulation = false
|
|---|
| 552 | UMIP: user-mode instruction prevention = false
|
|---|
| 553 | PKU protection keys for user-mode = false
|
|---|
| 554 | OSPKE CR4.PKE and RDPKRU/WRPKRU = false
|
|---|
| 555 | WAITPKG instructions = false
|
|---|
| 556 | AVX512_VBMI2 = false
|
|---|
| 557 | GFNI: Galois Field New Instructions = false
|
|---|
| 558 | VAES instructions = false
|
|---|
| 559 | VPCLMULQDQ instruction = false
|
|---|
| 560 | AVX512_VNNI = false
|
|---|
| 561 | AVX512_BITALG: bit count/shiffle = false
|
|---|
| 562 | AVX512: VPOPCNTDQ instruction = false
|
|---|
| 563 | BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
|
|---|
| 564 | RDPID: read processor D supported = false
|
|---|
| 565 | CLDEMOTE supports cache line demote = false
|
|---|
| 566 | MOVDIRI instruction = false
|
|---|
| 567 | MOVDIR64B intruction = false
|
|---|
| 568 | SGX_LC: SGX launch config supported = false
|
|---|
| 569 | AVX512_4VNNIW: neural network instrs = false
|
|---|
| 570 | AVX512_4FMAPS: multiply acc single prec = false
|
|---|
| 571 | fast short REP MOV = false
|
|---|
| 572 | PCONFIG = false
|
|---|
| 573 | Direct Cache Access Parameters (9):
|
|---|
| 574 | PLATFORM_DCA_CAP MSR bits = 0
|
|---|
| 575 | Architecture Performance Monitoring Features (0xa/eax):
|
|---|
| 576 | version ID = 0x2 (2)
|
|---|
| 577 | number of counters per logical processor = 0x2 (2)
|
|---|
| 578 | bit width of counter = 0x28 (40)
|
|---|
| 579 | length of EBX bit vector = 0x7 (7)
|
|---|
| 580 | Architecture Performance Monitoring Features (0xa/ebx):
|
|---|
| 581 | core cycle event not available = false
|
|---|
| 582 | instruction retired event not available = false
|
|---|
| 583 | reference cycles event not available = false
|
|---|
| 584 | last-level cache ref event not available = false
|
|---|
| 585 | last-level cache miss event not avail = false
|
|---|
| 586 | branch inst retired event not available = false
|
|---|
| 587 | branch mispred retired event not avail = false
|
|---|
| 588 | Architecture Performance Monitoring Features (0xa/edx):
|
|---|
| 589 | number of fixed counters = 0x3 (3)
|
|---|
| 590 | bit width of fixed counters = 0x28 (40)
|
|---|
| 591 | anythread deprecation = false
|
|---|
| 592 | XSAVE features (0xd/0):
|
|---|
| 593 | XCR0 lower 32 bits valid bit field mask = 0x00000003
|
|---|
| 594 | XCR0 upper 32 bits valid bit field mask = 0x00000000
|
|---|
| 595 | XCR0 supported: x87 state = true
|
|---|
| 596 | XCR0 supported: SSE state = true
|
|---|
| 597 | XCR0 supported: AVX state = false
|
|---|
| 598 | XCR0 supported: MPX BNDREGS = false
|
|---|
| 599 | XCR0 supported: MPX BNDCSR = false
|
|---|
| 600 | XCR0 supported: AVX-512 opmask = false
|
|---|
| 601 | XCR0 supported: AVX-512 ZMM_Hi256 = false
|
|---|
| 602 | XCR0 supported: AVX-512 Hi16_ZMM = false
|
|---|
| 603 | IA32_XSS supported: PT state = false
|
|---|
| 604 | XCR0 supported: PKRU state = false
|
|---|
| 605 | IA32_XSS supported: HDC state = false
|
|---|
| 606 | bytes required by fields in XCR0 = 0x00000240 (576)
|
|---|
| 607 | bytes required by XSAVE/XRSTOR area = 0x00000240 (576)
|
|---|
| 608 | XSAVE features (0xd/1):
|
|---|
| 609 | XSAVEOPT instruction = false
|
|---|
| 610 | XSAVEC instruction = false
|
|---|
| 611 | XGETBV instruction = false
|
|---|
| 612 | XSAVES/XRSTORS instructions = false
|
|---|
| 613 | SAVE area size in bytes = 0x00000000 (0)
|
|---|
| 614 | IA32_XSS lower 32 bits valid bit field mask = 0x00000000
|
|---|
| 615 | IA32_XSS upper 32 bits valid bit field mask = 0x00000000
|
|---|
| 616 | extended feature flags (0x80000001/edx):
|
|---|
| 617 | SYSCALL and SYSRET instructions = false
|
|---|
| 618 | execution disable = true
|
|---|
| 619 | 1-GB large page support = false
|
|---|
| 620 | RDTSCP = false
|
|---|
| 621 | 64-bit extensions technology available = true
|
|---|
| 622 | Intel feature flags (0x80000001/ecx):
|
|---|
| 623 | LAHF/SAHF supported in 64-bit mode = true
|
|---|
| 624 | LZCNT advanced bit manipulation = false
|
|---|
| 625 | 3DNow! PREFETCH/PREFETCHW instructions = false
|
|---|
| 626 | brand = "Intel(R) Celeron(R) CPU E3300 @ 2.50GHz"
|
|---|
| 627 | L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
|
|---|
| 628 | instruction # entries = 0x0 (0)
|
|---|
| 629 | instruction associativity = 0x0 (0)
|
|---|
| 630 | data # entries = 0x0 (0)
|
|---|
| 631 | data associativity = 0x0 (0)
|
|---|
| 632 | L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
|
|---|
| 633 | instruction # entries = 0x0 (0)
|
|---|
| 634 | instruction associativity = 0x0 (0)
|
|---|
| 635 | data # entries = 0x0 (0)
|
|---|
| 636 | data associativity = 0x0 (0)
|
|---|
| 637 | L1 data cache information (0x80000005/ecx):
|
|---|
| 638 | line size (bytes) = 0x0 (0)
|
|---|
| 639 | lines per tag = 0x0 (0)
|
|---|
| 640 | associativity = 0x0 (0)
|
|---|
| 641 | size (KB) = 0x0 (0)
|
|---|
| 642 | L1 instruction cache information (0x80000005/edx):
|
|---|
| 643 | line size (bytes) = 0x0 (0)
|
|---|
| 644 | lines per tag = 0x0 (0)
|
|---|
| 645 | associativity = 0x0 (0)
|
|---|
| 646 | size (KB) = 0x0 (0)
|
|---|
| 647 | L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
|
|---|
| 648 | instruction # entries = 0x0 (0)
|
|---|
| 649 | instruction associativity = L2 off (0)
|
|---|
| 650 | data # entries = 0x0 (0)
|
|---|
| 651 | data associativity = L2 off (0)
|
|---|
| 652 | L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
|
|---|
| 653 | instruction # entries = 0x0 (0)
|
|---|
| 654 | instruction associativity = L2 off (0)
|
|---|
| 655 | data # entries = 0x0 (0)
|
|---|
| 656 | data associativity = L2 off (0)
|
|---|
| 657 | L2 unified cache information (0x80000006/ecx):
|
|---|
| 658 | line size (bytes) = 0x40 (64)
|
|---|
| 659 | lines per tag = 0x0 (0)
|
|---|
| 660 | associativity = 4-way (4)
|
|---|
| 661 | size (KB) = 0x400 (1024)
|
|---|
| 662 | L3 cache information (0x80000006/edx):
|
|---|
| 663 | line size (bytes) = 0x0 (0)
|
|---|
| 664 | lines per tag = 0x0 (0)
|
|---|
| 665 | associativity = L2 off (0)
|
|---|
| 666 | size (in 512KB units) = 0x0 (0)
|
|---|
| 667 | Advanced Power Management Features (0x80000007/edx):
|
|---|
| 668 | temperature sensing diode = false
|
|---|
| 669 | frequency ID (FID) control = false
|
|---|
| 670 | voltage ID (VID) control = false
|
|---|
| 671 | thermal trip (TTP) = false
|
|---|
| 672 | thermal monitor (TM) = false
|
|---|
| 673 | software thermal control (STC) = false
|
|---|
| 674 | 100 MHz multiplier control = false
|
|---|
| 675 | hardware P-State control = false
|
|---|
| 676 | TscInvariant = false
|
|---|
| 677 | Physical Address and Linear Address Size (0x80000008/eax):
|
|---|
| 678 | maximum physical address bits = 0x24 (36)
|
|---|
| 679 | maximum linear (virtual) address bits = 0x30 (48)
|
|---|
| 680 | maximum guest physical address bits = 0x0 (0)
|
|---|
| 681 | Logical CPU cores (0x80000008/ecx):
|
|---|
| 682 | number of CPU cores - 1 = 0x0 (0)
|
|---|
| 683 | ApicIdCoreIdSize = 0x0 (0)
|
|---|
| 684 | (multi-processing synth): multi-core (c=2)
|
|---|
| 685 | (multi-processing method): Intel leaf 1/4
|
|---|
| 686 | (APIC widths synth): CORE_width=1 SMT_width=0
|
|---|
| 687 | (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
|
|---|
| 688 | (synth) = Intel Celeron E3000 (Wolfdale R0), 45nm
|
|---|
