#2074 closed defect (fixed)
cache.h(83): Assertion failed: "Validate()"
Reported by: | historic_bruno | Owned by: | ben |
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Priority: | Release Blocker | Milestone: | Alpha 14 |
Component: | Core engine | Keywords: | |
Cc: | Jan Wassenberg | Patch: |
Description
Reported on the forum: http://www.wildfiregames.com/forum/index.php?showtopic=17526
cache.h(83): Assertion failed: "Validate()" Assertion failed: "Validate()" Location: cache.h:83 (Initialize)
User's system_info.txt is attached.
Attachments (2)
Change History (11)
by , 11 years ago
Attachment: | system_info.txt added |
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comment:2 by , 11 years ago
Yes, I'd love to see those registers. This is a new CPU and it has an L3 cache. Perhaps caching is disabled in the BIOS? (That would be crazy, though)
I suppose it is possible CPUID4 is returning an empty/dummy entry, though those are skipped by us checking the type.
comment:3 by , 11 years ago
Hi Jan, it turns out that CPU also has an L4 cache! Whereas Philip pointed out the cache detection is hardcoded to maxlevels=3
right now. I'll just bump that to 4 :)
comment:5 by , 11 years ago
Very interesting, thanks! Have not come across mention of this. More info here: http://www.anandtech.com/show/6993/intel-iris-pro-5200-graphics-review-core-i74950hq-tested/3 Looks very powerful!
comment:6 by , 11 years ago
Jan: Out of interest, do you happen to be able to find information on what the new TLB descriptors (the "unknown"s in cpuid.txt, which aren't in our code either) mean? I couldn't find anything other than a post here mentioning b6 and c1 (and not the b5 that's on this processor) :-(
comment:7 by , 11 years ago
I've added B6 and C1 and will commit later today. The most recent manuals don't describe B5 - I've asked in that thread.
comment:9 by , 11 years ago
Here's the information on which the new entries are based:
reported: 0x63: unknown (= L1D huge page?) 0x03: data TLB: 4K pages, 4-way, 64 entries 0x76: instruction TLB: 2M/4M pages, fully, 8 entries 0xb5: unknown (= L1I?) TLB (0xC1, L2|U, 4*MiB, 8, 1024), http://www.realworldtech.com/haswell-cpu/2/ L1I, 4K, 4, 128 L1I, 2M, F, 8 http://www.realworldtech.com/haswell-cpu/5/ L1D, 4K, 4, 64 (0x03) L1D, 2M, 4, 32 (would be 0x5A) L1D, 1G, 4, 4 (0x63?) L2 4K/2M 8, 1024 (0xC1)
Philip suggested printing out register values for
CPUID2::GetDescriptors
andCPUID4::DetectCache
(tricky since it's an A13 release package), meanwhile waiting for user to run cpuid which may provide some clues. We could also enable the debug printing in hwdetect.js.If needed we can disable the
Validate()
call for A14.